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PDF PC87200 Data sheet ( Hoja de datos )
| Número de pieza | PC87200 | |
| Descripción | PC87200 PCI to ISA Bridge | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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August 1999
PC87200 PCI to ISA Bridge
1.0 General Description
The PC87200 Enhanced Integrated PCI-to-ISA bridge
works with an LPC chipset to provide ISA slot support. It is
a complement to the National Semiconductor PC8736x
Super I/O family.
2.0 Features
2.1 General
– Functionally compatible with Intel 82380AB
– 5.0 V tolerant PCI and ISA interfaces
– Slave mode serialized IRQ support for both quiet and
continuous modes
– PC/PCI DMA support
– 32-bit address decode for the 1MB BIOS ROM
– Supports ISA bus mastering
– 160-pin PQFP package
2.2 PCI-to-ISA Bridge
– PCI 2.1 compliant 33 MHz bus
– Supports PCI initiator-to-ISA and ISA master-to-PCI
cycle translations
– Subtractive agent for unclaimed transactions (see the
PROHIBIT signal description for exceptions)
– Parallel to Serial IRQ conversion including
IRQ3,4,5,6,7,9,10,11,12,14,15
– Supports 4 ISA slots directly without buffering
– Programmable ISA clock (8.33 to 11 MHz)
– Slow slew rate on edges
2.3 "PROHIBIT" functional support
– Disables PCI bus subtractive decoding when PRO-
HIBIT is asserted
Block Diagram
PCI Bus
Serialized IRQ
Interface
PCI to X-Bus / X-Bus to PCI Bridge
X-Bus
PC87200 Support
PCI Configuration
Registers
Decoding logic
X-Bus Arbiter
PROHIBIT
BPD#
Serial IRQ Slave
mode interface logic
ISA bus Target
Interface
ISA bus Master
Interface
PC/PCI DMA
Interface
PCPCIREQ#
PCPCIGNT#
ISA Bus
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
www.national.com
1 page  
3.0 Device Overview (Continued)
Table 1. SERIRQ Slave Generation Periods
SERIRQ
Period
Signal Generated
# of clocks past
Start
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
21:18
Reserved.
Reserved.
Reserved.
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Reserved.
IRQ9
IRQ10
IRQ11
IRQ12
Reserved.
IRQ14
IRQ15
IOCHK#
Reserved.
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
62,59,56, 53
3.4 PROHIBIT signal support
The chipset will use this signal to claim the BIOS first and
then deassert the "PROHIBIT" signal to configure the PCI
to ISA bridge to continue the boot sequence.
Special test mode support is provided by means of the
BPD# pin. When this test mode is active, the PC87200 will
enable positive memory decode during boot up to enable
the host to look for boot ROM on ISA card.
PROHIBIT will be a don’t care in this test mode at boot up
for the ROM BIOS range, but should function normally after
booting
3.5 PC/PCI DMA Interface Support
The PC87200 operates as a PC/PCI DMA Secondary Arbi-
tration Bridge. The PC87200 can pass all seven legacy ISA
bus DMA channel requests to the PC/PCI DMA Primary
Bus Arbiter using the channel passing protocol defined in
the Moble PC/PCI DMA Arbitration and Protocol Specifica-
tion (Revision 2.2). Figure 1 shows the topology of the
PC87200 PC/PCI DMA requests and grants:
The PC87200 converts the seven legacy ISA bus DMA
requests (DREQ0, 1, 2, 3, 5, 6 and 7) into a serial PC/PCI
DMA compliant REQ# sequence and converts the corre-
sponding PC/PCI DMA GNT# sequence into the appropri-
ate DMA acknowledge (DACK0-3, 5-7#). This PC/PCI DMA
expansion Channel Passing Protocol is illustrated
Figure 2.
PC/PCI DMA
Primary Bus
Arbiter
PCPCIGNT#
PCPCIREQ#
PC87200
PC/PCI DMA Interface Support
PCI Bus
Figure 1. PC87200 PC/PCI DMA Topology
ISA Bus
PCICLK
PCPCIREQ# start CH0
PCPCIGNT#
CH1 CH2 CH3 CH4 CH5 CH6 CH7
Figure 2. Channel Passing Protocol
start bit 0 bit 1 bit 2
5 www.national.com
5 Page 
5.0 Pin Descriptions (Continued)
Signal Name
DEVSEL#
PAR
SERR#
Pin No.
93
96
95
Type
I/O
t/s
I/O
t/s
O
OD
Description
PCI Device Select
DEVSEL# is asserted by a PCI slave, to indicate to a PCI master and subtractive
decoder that it is the target of the current transaction.
As an input, DEVSEL# indicates a PCI slave has responded to the current ad-
dress.
As an output, DEVSEL# is asserted one cycle after the assertion of FRAME#
and remains asserted to the end of a transaction as the result of a positive de-
code. DEVSEL# is asserted four cycles after the assertion of FRAME# if the
PC87200 is selected as the result of a subtractive decode. The subtractive de-
code sample point can be configured in F0 Index 41h[2:1]. These cycles are
passed to the ISA bus.
PCI Parity
PAR is the parity signal driven to maintain even parity across AD[31:0] and
C/BE[3:0]#.
The PC87200 drives PAR one clock after the address phase and one clock after
each completed data phase of write transactions as a PCI master. It also drives
PAR one clock after each completed data phase of read transactions as a PCI
slave.
PCI System Error
SERR# is pulsed by a PCI device to indicate an address parity error.
11 www.national.com
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PC87200.PDF ] | |
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