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Q-67106-H6514 Schematic ( PDF Datasheet ) - Siemens Semiconductor Group

Teilenummer Q-67106-H6514
Beschreibung PLL-Frequency Synthesizer PMB2306R/PMB2306T Version 2.2
Hersteller Siemens Semiconductor Group
Logo Siemens Semiconductor Group Logo 




Gesamt 35 Seiten
Q-67106-H6514 Datasheet, Funktion
ICs for Communications
PLL-Frequency Synthesizer
PMB2306R/PMB2306T Version 2.2
Data Sheet 02.97
T2306-0V22-D1-7600






Q-67106-H6514 Datasheet, Funktion
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9DD
9SS
9DD1
Positive supply voltage for serial control logic.
Ground for serial control logic.
Positive supply voltage for the preamplifiers, counters, phase
detector and charge pump.
9 11
9SS1 Ground for the preamplifiers, counters, phase detector and
charge pump.
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33
EN /LQH %XV (QDEOH
Enable line of the serial control with internal pull-up resistor.
When EN = H the input signals CLK and DA are disabled
internally. When EN = L the serial control is activated. The
received data are transferred into the latches with the positive
edge of the EN-signal.
44
DA /LQH %XV 'DWD
Serial data input with internal pull-up resistor. The last two bits
before the EN-signal define the destination address. In a byte-
oriented data structure the transmitted data have to end with
the EN-signal, i.e. bits to be filled in (don’t care) are transmitted
first.
55
CLK
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Clock line with internal pull-up resistor. The serial data are read
into the internal shift register with the positive edge (see pulse
diagram for serial data control).
77
MOD
0RGXOXV &RQWURO 2XWSXW for external dual modulus prescaler.
The modulus output is low at the beginning of the cycle. When
the a-counter has reached its set value, MOD switches to high.
When the n-counter has reached its set value, MOD switches to
low again, and the cycle starts from the top. When the prescaler
has the counter factor P or P + 1 (P for MOD = H, P +1 for MOD
= L), the overall scaling factor is NP + A. The value of the a-
counter must be smaller than that of the n-counter. The trigger
edge of the modulus signal to the input signal can be selected
(see programming tables and MOD
A, B) according to the needs of the prescaler. In single modulus
operation and for standby operation in dual modulus operation,
the output is low.
Semiconductor Group
6
02.97

6 Page









Q-67106-H6514 pdf, datenblatt
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0 0 1.3* 9DD = 5 V
0 15
1 0 10 not recommended
1 1 13** any application where
continuous lock detect required
* In general the shortest anti-backlash pulse gives the best system performance.
** No ABL (Anti-Backlash-Pulse) gating performed. This means, that at the LD output the anti-backlash pulse
will appear. In the other cases the anti-backlash pulse will be surpressed at the LD output.
Semiconductor Group
12
02.97

12 Page





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