Datenblatt-pdf.com


PC16550DN Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer PC16550DN
Beschreibung PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 22 Seiten
PC16550DN Datasheet, Funktion
June 1995
PC16550D Universal Asynchronous
Receiver Transmitter with FIFOs
General Description
The PC16550D is an improved version of the original 16450
Universal Asynchronous Receiver Transmitter (UART)
Functionally identical to the 16450 on powerup (CHARAC-
TER mode) the PC16550D can be put into an alternate
mode (FIFO mode) to relieve the CPU of excessive software
overhead
In this mode internal FIFOs are activated allowing 16 bytes
(plus 3 bits of error data per byte in the RCVR FIFO) to be
stored in both receive and transmit modes All the logic is on
chip to minimize system overhead and maximize system ef-
ficiency Two pin functions have been changed to allow sig-
nalling of DMA transfers
The UART performs serial-to-parallel conversion on data
characters received from a peripheral device or a MODEM
and parallel-to-serial conversion on data characters re-
ceived from the CPU The CPU can read the complete
status of the UART at any time during the functional opera-
tion Status information reported includes the type and con-
dition of the transfer operations being performed by the
UART as well as any error conditions (parity overrun fram-
ing or break interrupt)
The UART includes a programmable baud rate generator
that is capable of dividing the timing reference clock input
by divisors of 1 to (216b1) and producing a 16 c clock for
driving the internal transmitter logic Provisions are also in-
cluded to use this 16 c clock to drive the receiver logic The
UART has complete MODEM-control capability and a proc-
essor-interrupt system Interrupts can be programmed to
the user’s requirements minimizing the computing required
to handle the communications link
The UART is fabricated using National Semiconductor’s ad-
vanced M2CMOS process
Can also be reset to 16450 Mode under software control
Note This part is patented
Features
Y Capable of running all existing 16450 software
Y Pin for pin compatible with the existing 16450 except
for CSOUT (24) and NC (29) The former CSOUT and
NC pins are TXRDY and RXRDY respectively
Y After reset all registers are identical to the 16450 reg-
ister set
Y In the FIFO mode transmitter and receiver are each
buffered with 16 byte FIFO’s to reduce the number of
interrrupts presented to the CPU
Y Adds or deletes standard asynchronous communication
bits (start stop and parity) to or from the serial data
Y Holding and shift registers in the 16450 Mode eliminate
the need for precise synchronization between the CPU
and serial data
Y Independently controlled transmit receive line status
and data set interrupts
Y Programmable baud generator divides any input clock
by 1 to (216 b 1) and generates the 16 c clock
Y Independent receiver clock input
Y MODEM control functions (CTS RTS DSR DTR RI
and DCD)
Y Fully programmable serial-interface characteristics
5- 6- 7- or 8-bit characters
Even odd or no-parity bit generation and detection
1- 1 - or 2-stop bit generation
Baud generation (DC to 1 5M baud)
Y False start bit detection
Y Complete status reporting capabilities
Y TRI-STATE TTL drive for the data and control buses
Y Line break generation and detection
Y Internal diagnostic capabilities
Loopback controls for communications link
isolation
Break parity overrun framing error simulation
fault
Y Full prioritized interrupt system controls
Basic Configuration
TRI-STATE is a registered trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL C 8652
TL C 8652 – 1
RRD-B30M75 Printed in U S A






PC16550DN Datasheet, Funktion
4 0 Timing Waveforms (Continued)
Write Cycle
Applicable Only When ADS is Tied Low
Read Cycle
TL C 8652 – 5
Applicable Only When ADS is Tied Low
6
TL C 8652 – 6

6 Page









PC16550DN pdf, datenblatt
6 0 Pin Descriptions (Continued)
OUT 2 Output 2 Pin 31 This user-designated output that
can be set to an active low by programming bit 3 (OUT 2) of
the MODEM Control Register to a high level A Master Re-
set operation sets this signal to its inactive (high) state
Loop mode operation holds this signal in its inactive state In
the XMOS parts this will achieve TTL levels
RCLK Receiver Clock Pin 9 This input is the 16 c baud
rate clock for the receiver section of the chip
RD RD Read Pins 22 and 21 When RD is high or RD is
low while the chip is selected the CPU can read status
information or data from the selected UART register
Note Only an active RD or RD input is required to transfer data from the
UART during a read operation Therefore tie either the RD input per-
manently low or the RD input permanently high when it is not used
RI Ring Indicator Pin 39 When low this indicates that a
telephone ringing signal has been received by the MODEM
or data set The RI signal is a MODEM status input whose
condition can be tested by the CPU reading bit 6 (RI) of the
MODEM Status Register Bit 6 is the complement of the RI
signal Bit 2 (TERI) of the MODEM Status Register indicates
whether the RI input signal has changed from a low to a
high state since the previous reading of the MODEM Status
Register
Note Whenever the RI bit of the MODEM Status Register changes from a
high to a low state an interrupt is generated if the MODEM Status
Interrupt is enabled
RTS Request to Send Pin 32 When low this informs the
MODEM or data set that the UART is ready to exchange
data The RTS output signal can be set to an active low by
programming bit 1 (RTS) of the MODEM Control Register A
Master Reset operation sets this signal to its inactive (high)
state Loop mode operation holds this signal in its inactive
state
SIN Serial Input Pin 10 Serial data input from the commu-
nications link (peripheral device MODEM or data set)
SOUT Serial Output Pin 11 Composite serial data output
to the communications link (peripheral MODEM or data
set) The SOUT signal is set to the Marking (logic 1) state
upon a Master Reset operation
TXRDY RXRDY Pins 24 29 Transmitter and Receiver
DMA signalling is available through two pins (24 and 29)
When operating in the FIFO mode one of two types of DMA
signalling per pin can be selected via FCR3 When operat-
ing as in the 16450 Mode only DMA mode 0 is allowed
Mode 0 supports single transfer DMA where a transfer is
made between CPU bus cycles Mode 1 supports multi-
transfer DMA where multiple transfers are made continu-
ously until the RCVR FIFO has been emptied or the XMIT
FIFO has been filled
RXRDY Mode 0 When in the 16450 Mode (FCR0e0) or in
the FIFO Mode (FCR0e1 FCR3e0) and there is at least 1
character in the RCVR FIFO or RCVR holding register the
RXRDY pin (29) will be low active Once it is activated the
RXRDY pin will go inactive when there are no more charac-
ters in the FIFO or holding register
RXRDY Mode 1 In the FIFO Mode (FCR0e1) when the
FCR3e1 and the trigger level or the timeout has been
reached the RXRDY pin will go low active Once it is acti-
vated it will go inactive when there are no more characters
in the FIFO or holding register
TXRDY Mode 0 In the 16450 Mode (FCR0e0) or in the
FIFO Mode (FCR0e1 FCR3e0) and there are no charac-
ters in the XMIT FIFO or XMIT holding register the TXRDY
pin (24) will be low active Once it is activated the TXRDY
pin will go inactive after the first character is loaded into the
XMIT FIFO or holding register
TXRDY Mode 1 In the FIFO Mode (FCR0e1) when
FCR3e1 and there are no characters in the XMIT FIFO the
TXRDY pin will go low active This pin will become inactive
when the XMIT FIFO is completely full
VDD Pin 40 a5V supply
VSS Pin 20 Ground (0V) reference
WR WR Write Pins 19 and 18 When WR is high or WR is
low while the chip is selected the CPU can write control
words or data into the selected UART register
Note Only an active WR or WR input is required to transfer data to the
UART during a write operation Therefore tie either the WR input
permanently low or the WR input permanently high when it is not
used
XIN (External Crystal Input) Pin 16 This signal input is used
in conjunction with XOUT to form a feedback circuit for the
baud rate generator’s oscillator If a clock signal will be gen-
erated off-chip then it should drive the baud rate generator
through this pin
XOUT (External Crystal Output) Pin 17 This signal output is
used in conjunction with XIN to form a feedback circuit for
the baud rate generator’s oscillator If the clock signal will
be generated off-chip then this pin is unused
7 0 Connection Diagrams
Dual-In-Line Package
TL C 8652 – 17
Top View
Order Number PC16550DN
See NS Package Number N40A
12

12 Page





SeitenGesamt 22 Seiten
PDF Download[ PC16550DN Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
PC16550DPC16550D Universal Asynchronous Receiver/Transmitter with FIFOsNational Semiconductor
National Semiconductor
PC16550DPC16550D Universal Asynchronous Receiver/Transmitter With FIFOs (Rev. C)Texas Instruments
Texas Instruments
PC16550DNPC16550D Universal Asynchronous Receiver/Transmitter with FIFOsNational Semiconductor
National Semiconductor
PC16550DVPC16550D Universal Asynchronous Receiver/Transmitter with FIFOsNational Semiconductor
National Semiconductor
PC16550DVEFPC16550D Universal Asynchronous Receiver/Transmitter with FIFOsNational Semiconductor
National Semiconductor

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche