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PBL386502QNT Schematic ( PDF Datasheet ) - Ericsson

Teilenummer PBL386502QNT
Beschreibung Subscriber Line Interface Circuit
Hersteller Ericsson
Logo Ericsson Logo 




Gesamt 16 Seiten
PBL386502QNT Datasheet, Funktion
June 1999
PBL 386 50/2
Subscriber Line
Interface Circuit
Description
The PBL 386 50/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in Central Office Metering applications and other telecommunications
equipment. The PBL 386 50/2 has been optimized for low total line interface cost and
a high degree of flexibility in different applications.
The PBL 386 50/2 emulates resistive loop feed, programmable between 2x50
and 2x900 , with short loop current limiting adjustable to max 45 mA. In the current
limited region the loop feed is nearly constant current with a slight slope
corresponding to 2x30k.
A second, lower battery voltage may be connected to the device to reduce short
loop power dissipation. The SLIC automatically switches between the two battery
supply voltages without need for external components or external control.
The SLIC incorporates loop current, ground key and ring trip detection functions.
The PBL 386 50/2 is compatible with both loop and ground start signaling.
Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or
with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable
two-wire impedance, complex or real, is set by a simple external network.
Longitudinal voltages are suppressed by a feedback loop in the SLIC and the
longitudinal balance specifications meet Bellcore TR909 requirements.
The PBL 386 50/2 package options are 24-pin SSOP, 24-pin SOIC or 28-pin PLCC.
DT
DR
TIPX
RINGX
HP
VCC
VBAT2
VBAT
AGND
BGND
Two-wire
Interface
Ring Trip
Comparator
Ground Key
Detector
Line Feed
Controller
and
Longitudinal
Signal
Suppression
Off-hook
Detector
VF Signal
Transmission
Ring Relay
Driver
Input
Decoder
and
Control
RRLY
C1
C2
C3
DET
POV
PSG
PLC
LP
PLD
REF
VTX
RSN
Key Features
• 24-pin SSOP package
• Programmable two-wire signal
headroom for 2.2 Vrms metering
• High and low battery with automatic
switching
• Only +5 V feed in addition to battery
• Selectable transmit gain (0.5x or 0.25x)
• 70 mW on-hook power dissipation in
active state
• On-hook transmission
• Long loop battery feed tracks Vbat for
maximum line voltage
• No power-up sequence
• 43V open loop voltage @
-48V battery feed
• Constant loop voltage for line leakage
<5 mA (RLeak ~ >10 k@ -48V)
• Full longitudinal current capability
during on-hook state
• Analog over temperature protection
permits transmission while the
protection circuit is active
• Line voltage measurement
• Polarity reversal
• Ground key detector
• Tip open state with ring ground
detector
PBL 386 50/2
Figure 1. Block diagram.
PTG
24-pin SOIC, 24-pin SSOP, 28-pin PLCC
1






PBL386502QNT Datasheet, Funktion
PBL 386 50/2
Parameter
Ref
fig Conditions
Min Typ
Tip voltage (ground start)
Tip voltage (ground start)
Open circuit state loop current, I
LOC
Loop current detector
Programmable threshold, ILTh,
active, active reverse
Tip open state
Ground key detector
7 Active state, Tip lead open (S open), -4
Ring lead to ground through 150
Active state, tip lead to -48 V
-6
through 7 k(S closed), Ring
lead to ground through 150
R
L
=
0
-100
-2.2
-2.4
0
ILTh =
500
RLD
RLD in k, ILTh 7 mA
ILTh
=
500
RLD
0.85·ILTh ILTh
0.85·ILTh ILTh
Ground key detector threshold
(I and I difference to trigger ground key det.)
LTIPX
LRINGX
Line voltage measurement
10 16
Pulse width, tLVM
Ring trip comparator
Offset voltage, VDTDR
Input bias current, IB
Input common mode range, V , V
DT DR
Ring relay driver
Note 9
Source resistance, RS = 0
IB = (IDT + IDR)/2
5.5
-20
-200
V +1
Bat
0
-20
Saturation voltage, VOL
Off state leakage current, ILk
Digital inputs (C1, C2, C3)
IOL = 50 mA
VOH = 12 V
0.2
Input low voltage, VIL
Input high voltage, VIH
Input low current, I
IL
Input high current, IIH
Detector output (DET)
V = 0.5
IL
VIH = 2.5 V
0
2.5
Output low voltage
Internal pull-up resistor
IOL = 0.5 mA
15
Power dissipation (V = -48V, V = -32V)
Bat Bat2
P1
Open circuit state, C1, C2, C3 = 0, 0, 0
Active state, C1, C2, C3 = 0, 1, 0
10
P2
P
3
P
4
Power supply currents (VBat = -48V)
VCC current, ICC
VBat current, IBat
VCC current, ICC
VBat current, IBat
Power supply rejection ratios
Longitudinal current = 0 mA, I L=0 mA (on-hook) 70
R
L
=
300
(off-hook)
730
R
L
=
800
(off-hook)
360
Open circuit state
Active state
On-hook, Long Current = 0 mA
1.2
-0.1 -0.05
2.8
-1.5 -1.1
VCC to 2- or 4-wire port
VBat to 2- or 4-wire port
VBat2 to 2- or 4-wire port
Temperature guard
Active State
f = 1 kHz Vn = 100mV
30 42
36 45
40 60
Junction threshold temperature, T
JG
Thermal resistance
145
28-pin PLCC, θJP28plcc
24-pin SOIC, θJP24soic
24-pin SSOP, θJP24ssop
39
43
55
6
Max Unit
V
V
100 µA
1.15·ILTh mA
1.15·ILTh mA
22 mA
µs/V
20 mV
200 nA
-1 V
0.5 V
10 µA
0.5 V
VCC V
-50 µA
50 µA
0.7 V
k
15 mW
85 mW
mW
mW
2.0 mA
mA
4.0 mA
mA
dB
dB
dB
°C
°C/W
°C/W
°C/W

6 Page









PBL386502QNT pdf, datenblatt
PBL 386 50/2
Battery Feed
The PBL 386 50/2 SLIC emulate
resistive loop feed, programmable
between 2·50and 2·900 , with
adjustable current limitation. In the
current limited region the loop current
has a slight slope corresponding to
2·30 k, see figure 13 reference B.
The open loop voltage measured
between the TIPX and RINGX terminals
is tracking the battery voltage VBat. The
signalling headroom, or overhead voltage
VTRO, is programmable with a resistor ROV
connected between terminal POV on the
SLIC and ground. Please refer to section
“Programmable overhead voltage(POV)”.
The battery voltage overhead, VOH,
depends on the programmed signal
overhead voltage VTRO. VOH defines the
TIP to RING voltage at open loop
conditions according to VTR(at IL = 0 mA)
= |VBat| - VOH.
Refer to table 2 for typical values on
VOH and VOHVirt. The overhead voltage is
changed when the line current is ap-
proaching open loop conditions. To
ensure maximum open loop voltage,
even with a leaking telephone line, this
occurs at a line current of approximately
6 mA. When the overhead voltage has
changed, the line voltage is kept nearly
constant with a steep slope correspond-
ing to 2·25 (reference G in figure 13).
The virtual battery overhead, VOHVirt, is
defined as the difference between the
battery voltage and the crossing point of
all possible resistive feeding slopes, see
figure 13 reference J. The virtual battery
overhead is a theoretical constant
needed to be able to calculate the
feeding characteristics.
SLIC
VOH(typ)
[V]
VOHVirt(typ)
[V]
PBL 386 50/2 3.0 +VTRO 4.9 +VTRO
Table 2. Battery overhead.
The resistive loop feed (reference D in
figure 13) is programmed by connecting
a resistor, RSG, between terminals PSG
and VBAT according to the equation:
RFeed
=
RSG + 2·104
200
+
2RF
where RFeed is in for RSG and RF in .
The current limit (reference C in figure
13) is adjusted by connecting a resistor,
RLC, between terminal PLC and ground
according to the equation:
RLC
=
1000
ILProg + 4
where RLC is in kfor ILProg in mA.
A second, lower battery voltage may be
connected to the device at terminal
VBAT2 to reduce short loop power
dissipation. The SLIC automatically
switches between the two battery supply
voltages without need for external
control. The silent battery switching
occurs when the line voltage passes the
value |VB2| - 40·IL - (VOHVirt -1.3),
if IL > 6 mA.
For correct functionality it is important
to connect the terminal VBAT2 to the
second power supply via the diode DVB2
in figure 12.
An optional diode DBB connected
between terminal VB and the VB2 power
supply, see figure 12, will make sure that
the SLIC continues to work on the
second battery even if the first battery
voltage disappears.
If a second battery voltage is not used,
VBAT2 is connected to VBAT on the
SLIC and CVB2, DBB and DVB2 are removed.
Metering applications
For designs with metering applications
please contact Ericsson Microelectronics
for assistance.
CODEC Receive Interface
The PBL 386 50/2 SLIC have got a
completely new receive interface at the
four wire side which makes it possible to
reduce the number of capacitors in the
applications and to fit both single and
dual battery feed CODECs. The RSN
terminal, connecting to the CODEC
receive output via the resistor RRX, is dc
biased with +1.25V. This makes it
possible to compensate for currents
floating due to dc voltage differences
between RSN and the CODEC output
without using any capacitors. This is
done by connecting a resistor RR be-
tween the RSN terminal and ground.
With current directions defined as in
figure 14, current summation gives:
IRSN = IRT + IRRX + IRR =
1,25 + 1,25 VCODEC + 1,25
RT RRX RR
where VCODEC is the reference voltage of
the CODEC at the receive output.
From this equation the resistor RR can be
calculated as
RR
=
IRSN
1,25
RT
1,25
1,25
VCODEC
RRX
For values on IRSN, see table 3.
The resistor RR has no influence on the
ac transmission.
SLIC
PBL 386 50/2
IRSN [µA]
-155
Table 3. The SLIC internal bias current
with the direction of the current defined
as positive when floating into the terminal
RSN.
Programmable overhead voltage(POV)
With the POV function the overhead
voltage can be increased.
If the POV pin is left open the overhead
voltage is internally set to 3.2 VPeak in off-
12
11
10
9
8
7
6
5
4
3
2
1
0
0
10 20 30 40 50 60
Rov (K)
Figure 11. Programmable overhead voltage (POV). RL = 600 or .
off-hook
on-hook
12

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