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PBL38621-2 Schematic ( PDF Datasheet ) - Ericsson

Teilenummer PBL38621-2
Beschreibung Subscriber Line Interface Circuit
Hersteller Ericsson
Logo Ericsson Logo 




Gesamt 16 Seiten
PBL38621-2 Datasheet, Funktion
June 1999
PBL 386 21/2
Subscriber Line
Interface Circuit
Description
The PBL 386 21/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in DAML, FITL and other telecommunications equipment. The PBL
386 21/2 has been optimized for low total line interface cost and a high degree of
flexibility in different applications.
The PBL 386 21/2 has constant current feed, programmable to max. 30 mA.
A second lower battery voltage may be connected to the device to reduce short
loop power dissipation. The SLIC automatically switches between the two battery
supply voltages without need for external components or external control.
The SLIC incorporates loop current, ground key and ring trip detection functions.
The PBL 386 21/2 is compatible with loop start signaling.
Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or
with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable
the two-wire impedance, complex or real, is set by a simple external network.
Longitudinal voltages are suppressed by a feedback loop in the SLIC and the
longitudinal balance specifications meet Bellcore TR909 requirements.
The PBL 386 21/2 package options are 24-pin SSOP, 24-pin SOIC or 28-pin PLCC.
DT
DR
TIPX
RINGX
HP
VCC
VBAT2
VBAT
AGND
BGND
Two-wire
Interface
Ring Trip
Comparator
Ground Key
Detector
Line Feed
Controller
and
Longitudinal
Signal
Suppression
Off-hook
Detector
VF Signal
Transmission
Ring Relay
Driver
Input
Decoder
and
Control
RRLY
C1
C2
C3
DET
POV
PSG
PLC
LP
PLD
REF
VTX
RSN
Key Features
• 24-pin SSOP package
• High and low battery with automatic
switching
• 60 mW on-hook power dissipation in
active state
• On-hook transmission
• Long loop battery feed tracks Vbat for
maximum line voltage
• Only +5 V feed in addition to battery
• Selectable transmit gain (1x or 0.5x)
• No power-up sequence
• 44V open loop voltage @ -48V battery
feed
• Full longitudinal current capability
during on-hook state
• Analog over temperature protection
permits transmission while the
protection circuit is active
• Polarity reversal
• Integrated Ring Relay driver
• Ground key detector
• Programmable signal headroom
• -40 °C to +85 °C ambient temperature
range
PBL 386 21/2
Figure 1. Block diagram.
PTG
24-pin SOIC, 24-pin SSOP, 28-pin PLCC
1






PBL38621-2 Datasheet, Funktion
PBL 386 21/2
Parameter
Ref
fig Conditions
Min Typ
Loop current detector
Programmable threshold, ILTh
Ground key detector
ILTh =
500
RLD
RLD in k, ILTh 7 mA
0.85•ILTh
Ground key detector threshold
(ITIPX and IRINGX difference to trigger ground key det.)
Ring trip comparator
10
Offset voltage, VDTDR
Input bias current, IB
Input common mode range, VDT, VDR
Ring relay driver
Source resistance, RS = 0
IB = (IDT + IDR)/2
-20
-200
VBat+1
Saturation voltage, VOL
Off state leakage current, ILk
Digital inputs (C1, C2, C3)
IOL = 50 mA
VOH = 12 V
Input low voltage, VIL
Input high voltage, VIH
Input low current, IIL
Input high current, IIH
Detector output (DET)
VIL = 0.5
VIH = 2.5 V
0
2.5
Output low voltage
Internal pull-up resistor
IOL = 0.5 mA
Power dissipation (VBat = -48V, VBat2 = -17V)
P1
Open circuit state, C1, C2, C3 = 0, 0, 0
ILTh
16
0
-20
0.2
15
10
P2
P3
P4
Power supply currents (VBat = -48V)
VCC current, ICC
VBat current, IBat
VCC current, ICC
VBat current, IBat
Power supply rejection ratios
VCC to 2- or 4-wire port
VBat to 2- or 4-wire port
VBat2 to 2- or 4-wire port
Temperature guard
Junction threshold temperature, TJG
Thermal resistance
28-pin PLCC, θJP28plcc
24-pin SOIC, θJP24soic
24-pin SSOP, θJP24ssop
Active state, C1, C2, C3 = 0, 1, 0
Longitudinal current = 0 mA, I L=0 mA (on-hook)
RL = 300 (off-hook)
RL = 500 (off-hook)
60
290
145
Open circuit state
Active state
On-hook, Long Current = 0 mA
1.2
-0.1 -0.05
2.8
-1.5 -1.0
Active State
f = 1 kHz, Vn = 100mV
30 42
36 45
40 60
145
39
43
55
Max
Unit
1.15•ILTh mA
22 mA
20 mV
200 nA
-1 V
0.5 V
10 µA
0.5 V
VCC V
-50 µA
50 µA
0.7 V
k
15 mW
80 mW
mW
mW
2.0 mA
mA
4.0 mA
mA
dB
dB
dB
°C
°C/W
°C/W
°C/W
6

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PBL38621-2 pdf, datenblatt
PBL 386 21/2
switching occurs when the line voltage
passes the value
|VB2| - 40 · IL - VTRO = 3.6
For correct functionality it is important to
connect the terminal VBAT2 to the second
power supply via the diode DVB2 in figure 11.
An optional diode DBB connected between
terminal VB and the VB2 power supply, see
figure 11, will make sure that the SLIC
continues to work on the second battery
even if the first battery voltage disappears.
If a second battery voltage is not used,
VBAT2 is connected to VBAT on the SLIC
and CVB2, DBB and DVB2 are removed.
CODEC Receive Interface
The PBL 386 21/2 SLIC have got a
completely new receive interface at the
four wire side which makes it possible to
reduce the number of capacitors in the
applications and to fit both single and dual
battery feed CODECs. The RSN terminal,
connecting to the CODEC receive output
via the resistor RRX, is dc biased with +1.25V.
This makes it possible to compensate for
currents floating due to dc voltage
differences between RSN and the CODEC
output without using any capacitors. This is
done by connecting a resistor RR between
the RSN terminal and ground. With current
directions defined as in figure 13, current
summation gives:
IRSN = IRT + IRRX + IRR =
1,25 + 1,25 VCODEC + 1,25
RT RRX RR
where VCODEC is the reference voltage of the
CODEC at the receive output.
From this equation the resistor RR can be
calculated as
RR
=
IRSN
1,25
RT
1,25
1,25
VCODEC
RRX
For the value on IRSN, see table 3.
The resistor RR has no influence on the ac
transmission.
SLIC
PBL 386 21/2
IRSN [µA]
-55
Table 3. The SLIC internal bias current with
the direction of the current defined as
positive when floating into the terminal RSN.
Programmable overhead voltage(POV)
With the POV function the overhead
voltage can be increased.
If the POV pin is left open the overhead
voltage is internally set to 1.1 VPeak. The
overhead voltage is equal in on-hook and
off-hook. If a resistor ROV is connected
between the POV pin and AGND, the
overhead voltage can be set to higher
values, typical values can be seen in
figure 10. The ROV and corresponding
VTRO (signal headroom) are typical values
for THD <1% and the signal frequency
1000Hz.
Observe that the 4-wire output terminal VTX
can not handle more than 3.2 VPeak. So if the
gain 2-wire to 4-wire is 0dB, 3.2 VPeak is
maximum also for the 2-wire side. Signal
levels between 3.2 and 6.4 VPeak on the
2-wire side can be handled with the PTG
shorted so that the gain G2-4S become
-6.02dB. Please note that the 2-wire
impedance, RR and the 4-wire to 4-wire
gain has to be recalculated if the PTG is
shorted.
Please note that the maximum signal
current at the 2-wire side can not be
greater than 9 mA.
How to use POV:
1. Decide what overhead
voltage(VTRO) is needed. The POV
function is only needed if the
overhead voltage exceeds 1.1 VPeak
2. In figure 10 the corresponding ROV
for the decided VTRO can be found.
3. If the overhead voltage exceeds
3.2 VPeak, the G2-4S gain has to be
changed to -6.02dB by connecting
the PTG pin to AGND. Please note
that the 2-wire impedance, RR and
the 4-wire to 4-wire gain has to be
recalculated.
Analog Temperature Guard
The widely varying environmental
conditions in which SLICs operate may
lead to the chip temperature limitations
being exceeded. The PBL 386 21/2 SLIC
reduce the dc line current when the chip
temperature reaches approximately 145°C
and increases it again automatically when
the temperature drops. Accordingly trans-
mission is not lost under high ambient
temperature conditions.
The detector output, DET, is forced to a
logic low level when the temperature guard
is active.
Loop Monitoring Functions
The loop current, ground key and ring trip
detectors report their status through a com-
mon output, DET. The detector to be
connected to DET is selected via the three
bit wide control interface C1, C2 and C3.
Please refer to section Control Inputs for a
description of the control interface.
Loop Current Detector
The loop current detector is indicating that
the telephone is off hook and that current is
flowing in the loop by putting the output
DET to a logical low level when selected.
The loop current threshold value, ILTh, at
which the loop current detector changes
state is programmable by selecting the
value of resistor RLD. RLD connects between
pin PLD and ground and is calculated
according to
RLD
=
500
ILTh
The current detector is internally filtered
and is not influenced by the ac signal at the
two wire side.
Ground Key Detector
The ground key detector is indicating when
the ground key is pressed (active) by putting
the output pin DET to a logical high level
when selected. The ground key detector
circuit senses the difference in TIPX and
RINGX currents. When the current at the
RINGX side exceeds the current at the
TIPX side with the threshold value the
detector is triggered. For threshold current
values, please refer to the datasheet.
Ring Trip Detector
Ring trip detection is accomplished by
connecting an external network to a
comparator in the SLIC with inputs DT and
DR. The ringing source can be balanced or
unbalanced superimposed on VB or GND.
The unbalanced ringing source may be
applied to either the ring lead or the tip lead
with return via the other wire. A ring relay
driven by the SLIC ring relay driver connects
the ringing source to tip and ring.
The ring trip function is based on a polarity
change at the comparator input when the
line goes off-hook. In the on-hook state no
dc current flows through the loop and the
voltage at comparator input DT is more
positive than the voltage at input DR. When
the line goes off-hook, while the ring relay
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