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PBL3853SO-T Schematic ( PDF Datasheet ) - Ericsson

Teilenummer PBL3853SO-T
Beschreibung Universal Speech Circuit
Hersteller Ericsson
Logo Ericsson Logo 




Gesamt 16 Seiten
PBL3853SO-T Datasheet, Funktion
May 1996
PBL 3853
Universal Speech Circuit
Description
The PBL 3853 is a biopolar integrated speech circuit with specific parameters making
it highly suitable to be used as a line interface and speech circuit in a telephone line
powered electronic payphone. Emphasis has been put on low current consumption in
the IC thus facilitating that a greater part of the available line current can be used to
power other electrical functions in the design. From a minimum line current of
16 mA, 12 mA at 4.5 V can be used to power auxiliary functions. The circuit can
optionally create an active impedance towards the telephone line, set by external
passive components, to reduce the current consumption for the transmitted signal.
The circuit is designed to be used with a low impedance dynamic microphone but can
be used with an electret type as well. The receiver drives a low ohm dynamic
transducer directly. External clamping diodes are required on the receiver output.
Both transmitter and receiver can be muted separately (receiver cut off). Line length
regulation of the gain is possible in both receiver and transmitter. It is also possible to
use the circuit without regulation. Payphone tones and confidence tone in the recei-
ver at DTMF dialling can be injected directly into the receiver amplifier where their
levels are not affected by line length regulation and without the signal going out on
the line. All pin numbers refer to DIP package unless otherwise noted.
Key Features
Low own current consumption
Can operate both with active and
passive impedance towards the line
Derives a high current from the line
for auxiliary functions, 12 mA at
16 mA line current
Separate mute inputs for transmitter
and receiver (receiver cut off)
Line length regulation possible (line
loss compensation
Comes in 18 pin DIP and 20-pin SO
package
High line current operation, max.
130 mA
Especially suitable for payphone
applications
DTMF - confidence tone input
Excellent RFI performance
PBL 3853
5
4
+V
10
1
9
-
+
+
-
7
+
-8
12
MA
13
Rx
18
Tx
16
18-pin plastic DIP
6 14
11 3
2
17
15
Figure 1. Block diagram. Pin numbers in all figures refer to DIP package.
20-pin plastic SO






PBL3853SO-T Datasheet, Funktion
PBL 3853
Functional Description
Design Procedure
The first decision to make is, how much
current is needed at what VDC and how
much line current is available at longest
line length.
1. Set the circuit impedance to the line,
either active or passive. C3 should be
big enough to give low impedance
compared with R1 in the telephone
speech frequency band. Too large C3
will make the ”start up” slow.
2. Set the DC-characteristic that is
required in the PTT specification, or in
case of a system telephone design, in
the PABX specification (R5).
3. If the line length regulation (line loss
compensation) is used, set the attac
point where it should start (RC and
RD). Using the line length regulation
makes it in most cases easier to
achieve the gain/line length mask in
both transmitter and receive function.
Note, that in some countries the line
length regulation is not allowed.
4. Set the transmitter gain and
frequency response. See text for the
clipping feature.
5. Set the receiver gain and frequency
response.
6. Adjust the side tone balancing
network.
7. Apply the RFI suppression
components in case necessary. In two
piece telephones the often ”helically”
wound cord acts as an aerial where
especially the microphone input with
its high gain and input impedance is
the more sensitive.
Impedance to the Line
The AC-impedance to the line is set by
R1 (+ R2 if active impedance is used)
and C2. See figure 4. The circuits
relatively high parallel impedance will
influence it to some extent. At low
frequencies the influence of the C can
3
not be neglected. Series resistance of
the C3 that is dependent on temperature
and quality will cause that some of the
line signal will enter pin 4 and generate a
closed loop in the transmitter amplifier
that will create an active impedance thus
lowering the impedance to the line. The
impedance at high frequencies is set by
C2 that also acts as a RFI supressor.
In many specifications the R1 is
specified as a complex network. See
figure 6 b) in the example. In case a) the
error signal entering pin 4 is set by the
ratio RS/R1 (909 Swedish spec.),
where in case b) the ratio at high
frequency will be RS/220 because the
820 resistor is bypassed by a
capacitor. To help up this situation the
complex network capacitor is connected
directly to ground, case c) making the
ratio RS/(220+820) and thus lessening
the influence of the error signal. To save
current the circuit can be implemented
to have an active impedance to the line,
the level is set by resistors R1 and R2.
When an active impedance is used the
transmitter (see figure 16) amplifier does
not feel its own active output-impedance
thus using less current to create output
swing to the line. Case c) above can not
be used together with active impedance.
Do not use the active impedance if not
necessary, it complicates things greatly.
A full mathematical expression is
found under Detailed Description.
DC - Characteristics
The DC - characteristic that a telephone
set has to fulfill is mainly given by the
network administrator. Following para-
meters are useful to know when the DC
behaviour of the telephone is to be set:
• The voltage of the feeding system
• The line feeding resistance 2 x
• The maximum current from the line at
zero line length
• The minimum current at which the
telephone has to work (basic
function)
• The lowest and highest voltage
across the telephone
The DC-characteristic of the circuit is
a function of the voltage on pin 4. There
is also a possibility to adjust the DC-
characteristic with resistors (dc-voltage)
at pin 5 (RA and RB in figure 4). Note
that altering the DC-characteristic slope
will also influence the line length
regulation (when used) and thus the gain
of both transmitter and receiver. A closer
mathematical study is done under
Detailed Description.
Line Length Regulation
The line length regulation is to
compensate the gain in both transmitter
and receiver with changing line length
(impedance). The dynamic range of
regulation is 6 dB. The starting point of
the regulation can be set by RC and RD
that take the information from the circuits
supply voltage which actually mirrors the
line current value in voltage. In case line
length regulation is not required it can be
omitted either in the high or in the low
gain mode (6 dB range of regulation).
a) Real impedance
b) Complex impedance
c) b)
Example: b)
A complex network
220+ 820//115nF
a)
R1
Rs
1
+Line
C2
PBL3853
4
Circuit supply
I=0.3mA
VF
The complex network should
be connected to the speech
circuit like shown in c). See text.
C3
Figure 6. AC-impedance, to the line.
6
+Line
C2
R1 PBL 3853
R1
Circuit supply
VF
I=0.3mA
4
C3
The voltage across the circuit can be increased
by method shown above without influencing the
impedance towards the line.
Figure 7. Adjusting voltage level across
the circuits.

6 Page









PBL3853SO-T pdf, datenblatt
PBL 3853
Comments to the Reference
Figure for PBL 3853 Test Set
up (fig.4) Regarding the
External DC-Supply (VDC).
This schematic is a specific application
of the PBL 3853, where the main
objective is to optimize the usage of the
line current so that of 16 mA line current
12 mA can be taken out to feed auxiliary
functions. Typical line voltage 6.0 V at
20 mA line current (with a transmitter
signal swing of 1.8 Vpeak).
It would be possible to save some
more current (50mA) by instead of
increasing the DC-characteristic towards
the line with low ohmic Rc and Rd (the
sum 41k) make these larger
(68k+33k=101k) and lift the DC-char.
with Rb instead (see fig.7). The gain of
this is questionable because the need of
an additional resistor.
It ought to be understood that these
12 mA charge current into VDC out of
16 mA line current can only be acchie-
ved in no signal condition, both transmit-
ter and receiver. In case there is a
transmitted signal above a certain (low)
amplitude, it will cause breaks in the 12 mA
VDC charge current during a part or the
whole time of the negative half periodes
of the signal on the line. This means that
the filtered VDC will have a lower usable
current output. Is the said signal on the
line large, it will cause an absense of the
charge current half of the time and the
useful current will sink to 6 mA.
(See fig. 15). A similar thing will happen
at receiving as at transmitting but on top
of that, the current to the receiver which
is taken from VDC will leave even less
current available from VDC. The speech
functions and with them the VDC output
will die below 16 mA line current. There
is an unintentional effect that might
cause puzzlement. Just below 16 mA
line current the VDC will come into
function and will be operating when a
high signal is on the line. With a high
signal on the line half of the set current,
in this case 6 mA, can be taken out. The
possible available current out from VDC
will increase with increasing line current
and the margin to, that a signal on the
line has the effect of decreasing the
available current out from VDC, will
increase in the same extent as the line
voltage increases.
Figure 4 shows only one of the many
ways to use the circuit to generate the
VDC supply. The conditions for
dimensioning the VDC are set by the
available line voltage and line current,
what voltage respectively current the V
DC
supply has to deliver or actually the
difference between the line voltage and
V out respectively line current contra
DC
the possible output current from VDC. It is
possible to minimize these differencies
somewhat but it requires more complex
solutions, on the other hand if the
requirement to keep the voltage and
current difference as small as possible is
not of utmost importance it is possible to
create simpler solutions than what is
shown in the figure 4.
In case there is a need to minimize the
voltage difference between line and VDC
it can be influenced as follows. To start
with, the level that sets which way the
current will go, either through T1 to VDC
or through T2 to ground, has to be
altered. It is done easiest by adding a
shunt regulator between the collector of
T1 and pin 18 on the circuit. The VDC is
still taken at the collector of T1,
see fig. 20.
In the most simple case the shunt
regulator can be a diode (eventually a
Shottky diode) maybe with an addition of
a resistor between pin 18 and -line to
keep somewhat constant voltage across
the diode. Unfortunable the voltage can
not be increased more than a couple of
hundred millivolts before the function
that is to provent the T1 from saturating
regarding the voltage across it would
disappear and which in is turn would
result that the negative half periodes of
the signal would be clipped with a
massive distortion as a result. What has
to be done at the same time to come
further in this matter is to make the
voltage drop smaller across R13 (also to
use a T1 with low sat.voltage). This
requires that the sense level of which
voltage has to be across R13 is altered.
The voltage across R13 is one diode
drop plus the voltage drop across R12.
What can be done is to substract some
of the diode drop, see fig. 21.
Observe that the circuitry needs a
recalculation of several components
especially R13. How far it is possible to
come, by decreasing the gap between
Vline and VDC depends on spread figures
and temperature requirement.
The difference between the line
current and current out from VDC is
possible to alter but only to minor extent.
Line with signal
TR2 control
level
DC- supply 4.5V
TR1
TR1 conducting. DC- supply charged constantly.
Line with signal
TR2 control
level
DC- supply 4.5V
TR1
TR2 conducts. DC- supply charge
interrupted during these periodes.
Figure 18.
12
I1
R12
4 PBL3853
Circuit supply
VF
I=0.3mA
19
to gain reg.
with line length
VD
-
7.5k
+
R1 Vx
1.2V + 13k
37.5k
15k
2xVD
+
6
45k
C1 5 2.5k
10k
+
8.77k
-
Mic. 12 1.2V +
15k 7.5k
13 A1
+
R2 1.2V
10 11 3 14
+
-
36k
2
-
17 15
VF
RA
+
C3
RB
C4
R3 C5
R4
R5
R13 IL VL
IDC
7 T2
+ 8 T1
18 VDC
16
4.5V
C2
Figure 19 . Functional Diagram.

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