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PBD35171 Schematic ( PDF Datasheet ) - Ericsson

Teilenummer PBD35171
Beschreibung Stepper Motor Drive Circuit
Hersteller Ericsson
Logo Ericsson Logo 




Gesamt 10 Seiten
PBD35171 Datasheet, Funktion
February 1999
PBD 3517/1
Stepper Motor
Drive Circuit
Description
PBD 3517/1 is a bipolar, monolithic, integrated circuit, intended to drive a stepper motor
in a unipolar, bilevel way.
One PBD 3517/1 and a minimum of external components form a complete control
and drive unit for LS-TTL- or microprocessor-controlled stepper motor system for
currents up to 500mA. The driver is suited for applications requiring least-posssible RFI.
Motor performance can be increased by operating in a bilevel drive mode. This
means that a high voltage pulse is applied to the motor winding at the beginning of a
step, in order to give a rapid rise of current.
Key Features
• Complete driver and phase logic on
chip
• 2 x 350 mA continuous-output current
• Half- and full-step mode generation
• LS-TTL-compatible inputs
• Bilevel drive mode for high step rates
• Voltage-doubling drive possibilities
• Half-step position-indication output
• Minimal RFI
• 16-pin plastic DIP package or 16 pin
small outline wide body
PBD 3517/1
RC Mono
F-F
VCC
PQR
STEP
DIR
HSM
INH
OA
OB
Phase PA
Logic
PB
Figure 1. Block diagram.
VSS
LA
LB
PB2
PB1
PA2
PA1
16-pin plastic DIP
GND 16-pin SO (wide body)
1






PBD35171 Datasheet, Funktion
PBD 3517/1
Functional Description
The circuit, PBD 3517/1, is a high
perform-ance motor driver, intended to
drive a stepper motor in a unipolar, bilevel
way. Bilevel means that during the first
time after a phase shift, the voltage
across the motor is increased to a second
voltage supply, VSS, in order to obtain a
more-rapid rise of current, see figure 11.
The current starts to rise toward a
value which is many times greater than
the rated winding current. This compen-
sates for the loss in drive current and loss
of torque due to the back emf of the
motor.
After a short time, tOn, set by the
monostable, the bilevel output is switched
off and the winding current flows from the
V supply, which is chosen for rated
MM
winding current. How long this time must
be to give any increase in performance is
determined by V voltage and motor
SS
data, the L/R time-constant.
In a low-voltage system, where high
motor performance is needed, it is also
possible to double the motor voltage by
adding a few external components, see
figure 14.
The time the circuit applies the higher
voltage to the motor is controlled by a
monostable flip-flop and determined by
the timing components RT and CT.
The circuit can also drive a motor in
traditional unipolar way.
An inhibit input (INH) is used to switch
off the current completely.
Logic inputs
All inputs are LS-TTL compatible. If any
of the logic inputs are left open, the
circuit will accept it as a HIGH level. PBD
3517/1 contains all phase logic
necessary to control the motor in a
proper way.
STEP — Stepping pulse
One step is generated for each negative
edge of the STEP signal. In half-step
mode, two pulses will be required to move
one full step. Notice the set up time, ts, of
DIR and HSM signals. These signals
must be latched during the negative edge
of STEP, see timing diagram, figure 3.
DIR — Direction
DIR determines in which direction steps
will be taken. Actual direction depends on
motor and motor connections. DIR can be
changed at any time, but not simultan-
eously with STEP, see timing diagram,
figure 3.
HSM determines whether the motor will
be controlled in full-step or half-step
mode. When pulled low, a step-pulse will
correspond to a half step of the motor.
HSM can be changed at any time, but not
simultaneously with STEP, see timing
diagram, figure 3.
VSS
VMM
+ 5V
VCC
CMOS, TTL-LS
Input / Output-Device
STEP
CW / CCW
HALF / FULL STEP
NORMAL /INHIBIT
(Optional Sensor)
GND
GND (VCC)
RC 12
R9 R8 RT CT
STEP 7
DIR 6
HSM 10
INH 11
OA 9
OB 8
Mono
F-F
Phase PA
Logic
PB
++ +
C3 C4 C5
VCC
VSS
16 15
PQR
D3
PBD 3517/1
13 LA
14 LB
1 PB2
2 PB1
5 PA2
4 PA1
3 GND
D2 D1
R11 R10
MOTOR
D3-D6
D3-D6 are
UF 4001 or
BYV 27
trr < 100 ns
GND (VMM,VSS)
VMM
+ 5V
VCC
CMOS, TTL-LS
Input / Output-Device
STEP
CW / CCW
HALF / FULL STEP
NORMAL /INHIBIT
(Optional Sensor)
GND
GND (VCC)
RC 12
R9 R8 RT CT
STEP 7
DIR 6
HSM 10
INH 11
OA 9
OB 8
Mono
F-F
Phase PA
Logic
PB
++
R1
C3 C4
VCC
VSS
16 15
PQR
PBD 3517/1
D1
13 LA
14 LB
1 PB2
2 PB1
5 PA2
4 PA1
Q1
C1
Q3
R10
R2
Equal to
Phase A R12
1/2 MOTOR
R13
R4
Q5
Q6
R5
3 GND
GND (VMM,VSS)
6
Figure 14.
Typical
application.
Figure 15. Voltage
doubling with
external
transistors.

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