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PALLV22V10-10PC Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer PALLV22V10-10PC
Beschreibung Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device
Hersteller Lattice Semiconductor
Logo Lattice Semiconductor Logo 




Gesamt 19 Seiten
PALLV22V10-10PC Datasheet, Funktion
PALLV22V10 COM'L: -7/10/15
PALLV22V10Z
IND: -15
IND: -25
PALLV22V10 and PALLV22V10Z Families
Low-Voltage (Zero Power) 24-Pin EE CMOS
Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
x Low-voltage operation, 3.3 V JEDEC compatible
— VCC = + 3.0 V to 3.6 V
x Commercial and industrial operating temperature range
x 7.5-ns tPD
x Electrically-erasable technology provides reconfigurable logic and full testability
x 10 macrocells programmable as registered or combinatorial, and active high or active low to
match application needs
x Varied product term distribution allows up to 16 product terms per output for complex
functions
x Global asynchronous reset and synchronous preset for initialization
x Power-up reset for initialization and register preload for testability
x Extensive third-party software and programmer support
x 24-pin SKINNY DIP and 28-pin PLCC packages save space
GENERAL DESCRIPTION
The PALLV22V10 is an advanced PAL® device built with low-voltage, high-speed, electrically-
erasable CMOS technology.
The PALLV22V10Z provides low voltage and zero standby power. At 30 µA maximum standby
current, the PALLV22V10Z allows battery powered operation for an extended period.
The PALLV22V10 device implements the familiar Boolean logic transfer function, the sum of
products. The PAL device is a programmable AND array driving a fixed OR array. The AND array
is programmed to create custom product terms, while the OR array sums selected terms at the
outputs.
The product terms are connected to the fixed OR array with a varied distribution from 8 to 16
across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell.
Each macrocell can be programmed as registered or combinatorial, and active high or active low.
The output configuration is determined by two bits controlling two multiplexers in each macrocell.
Publication# 18956 Rev: F
Amendment/0
Issue Date: September 2000






PALLV22V10-10PC Datasheet, Funktion
Quality and Testability
The PALLV22V10 offers a very high level of built-in quality. The erasability of the CMOS
PALLV22V10 allows direct testing of the device array to guarantee 100% programming and
functional yields.
Technology
The high-speed PALLV22V10 is fabricated with Vantis’ advanced electrically-erasable (EE) CMOS
process. The array connections are formed with proven EE cells. Inputs and outputs are designed
to be 3.3-V and 5-V device compatible. This technology provides strong input-clamp diodes,
output slew-rate control, and a grounded substrate for clean switching.
Zero-Standby Power Mode
The PALLV22V10Z features a zero-standby power mode. When none of the inputs switch for an
extended period (typically 30 ns), the PALLV22V10Z will go into standby mode, shutting down
most of its internal circuitry. The current will go to almost zero (ICC <30 µA). The outputs will
maintain the states held before the device went into the standby mode.
If a macrocell is used in registered mode, switching pin CLK/I0 will not affect standby mode status
for that macrocell. If a macrocell is used in combinatorial mode, switching pin CLK/I0 will affect
standby mode status for that macrocell.
This feature reduces dynamic ICC proportionally to the number of registered macrocells used. If all
macrocells are used as registers and only CLK/I0 is switching, the device will not be in standby
mode, but dynamic ICC will typically be <2 mA. This is because only the CLK/I0 buffer will draw
current. The use of combinatorial macrocells will add on average 5 mA per macrocell (at 25 MHz)
under these same conditions.
When any input switches, the internal circuitry is fully enabled, and power consumption returns
to normal. This feature results in considerable power savings for operation at low to medium
frequencies.
Product-Term Disable
On a programmed PALLV22V10Z, any product terms that are not used are disabled. Power is cut
off from these product terms so that they do not draw current. Product-term disabling results in
considerable power savings. This saving is greater at the higher frequencies.
Further hints on minimizing power consumption can be found in a separate document entitled,
Minimizing Power Consumption with Zero-Power PLDs.
6 PALLV22V10 and PALLV22V10Z Families

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PALLV22V10-10PC pdf, datenblatt
SWITCHING WAVEFORMS
Input or
Feedback
Combinatorial
Output
VT
tPD
VT
18956D-007
Input or
Feedback
Clock
Registered
Output
a. Combinatorial output
VT
tS tH
VT
tCO
VT
18956D-008
b. Registered output
Clock
tWH
VT
tWL
c. Clock width
18956D-009
Input
Output
VT
tER tEA
VOH - 0.5V
VOL + 0.5V
VT
18956D-010
d. Input to output disable/enable
Input
Asserting
Asynchronous
Reset
Registered
Output
Clock
tARW
VT
tAR
VT
tARR
VT
Input
Asserting
Synchronous
Preset
Clock
Registered
Output
e. Asynchronous reset
18956D-011
VT
tS tH tSPR
VT
tCO
VT
18956D-012
f. Synchronous preset
Notes:
1. VT = 1.5 V for inputs signals and VCC/2 for outputs signals.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns to 5 ns typical.
12 PALLV22V10 and PALLV22V10Z Families

12 Page





SeitenGesamt 19 Seiten
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