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PALLV16V8-10JC Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer PALLV16V8-10JC
Beschreibung Low Voltage/ Zero Power 20-Pin EE CMOS Universal Programmable Array Logic
Hersteller Lattice Semiconductor
Logo Lattice Semiconductor Logo 




Gesamt 22 Seiten
PALLV16V8-10JC Datasheet, Funktion
FINAL
COM’L:-10
IND:-20
PALLV16V8-10 and PALLV16V8Z-20
Low Voltage, Zero Power 20-Pin EE CMOS
Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
x Low-voltage operation, 3.3 V JEDEC compatible
— VCC = +3.0 V to +3.6 V
x Pin and function compatible with all 20-pin PAL® devices
x Electrically-erasable CMOS technology provides reconfigurable logic and full testability
x Direct plug-in replacement for the PAL16R8 series
x Designed to interface with both 3.3-V and 5-V logic
x Outputs programmable as registered or combinatorial in any combination
x Programmable output polarity
x Programmable enable/disable control
x Preloadable output registers for testability
x Automatic register reset on power up
x Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
x Extensive third-party software and programmer support
x Fully tested for 100% programming and functional yields and high reliability
GENERAL DESCRIPTION
The PALLV16V8 is an advanced PAL device built with low-voltage, high-speed, electrically-erasable
CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells
provide a universal device architecture. The PALLV16V8 will directly replace the PAL16R8, with the
exception of the PAL16C1.
The PALLV16V8Z provides zero standby power and high speed. At 30-µA maximum standby
current, the PALLV16V8Z allows battery powered operation for an extended period.
The PALLV16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can
always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate cells
in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions. The sum
of these products feeds the output macrocell. Each macrocell can be programmed as registered or
combinatorial with an active-high or active-low output. The output configuration is determined by
two global bits and one local bit controlling four multiplexers in each macrocell.
Publication# 17713 Rev: E
Amendment/0
Issue Date: November 1998






PALLV16V8-10JC Datasheet, Funktion
OE
DQ
CLK Q
a. Registered active low
OE
DQ
CLK Q
b. Registered active high
c. Combinatorial I/O active low
VCC
d. Combinatorial I/O active high
VCC
Note 1
e. Combinatorial output active low
Note 1
f. Combinatorial output active high
Notes:
. Feedback is not available on pins 15 and 16 in the
combinatorial output mode.
. The dedicated-input configuration is not available
on pins 15 and 16.
g. Dedicated input
Adjacent I/O pin
Note 2
17713D-5
Figure 2. Macrocell Configurations
6 PALLV16V8-10 and PALLV16V8Z-20 Families

6 Page









PALLV16V8-10JC pdf, datenblatt
CAPACITANCE 1
Parameter
Symbol
Parameter Description
Test Condition
Typ Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC - 3.3 V, TA = 25°C,
COUT
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
5 pF
8 pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 1
Parameter
Symbol
Parameter Description
-10
Min Max
Unit
tPD Input or Feedback to Combinatorial Output (Note 2)
10 ns
tS Setup Time from Input or Feedback to Clock
7 ns
tH Hold Time
0 ns
tCO Clock to Output
7 ns
tWL LOW
Clock Width
tWH HIGH
6 ns
6 ns
External Feedback
1/(tS + tCO)
71.4
fMAX
Maximum Frequency
(Notes 2 and 3)
Internal Feedback (fCNT
1/(tS + tCF)
83.3
No Feedback
1/(tS + tH)
83.3
MHz
MHz
MHz
tPZX OE to Output Enable
10 ns
tPXZ OE to Output Disable
10 ns
tEA Input to Output Enable Using Product Term Control
12 ns
tER Input to Output Disable Using Product Term Control
12 ns
Notes:
1. See “Switching Test Circuit” for test conditions.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
frequency may be affected.
3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) - tS.
12 PALLV16V8-10 (Com’l)

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