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PALCE29MA16 Schematic ( PDF Datasheet ) - Advanced Micro Devices

Teilenummer PALCE29MA16
Beschreibung 24-Pin EE CMOS Programmable Array Logic
Hersteller Advanced Micro Devices
Logo Advanced Micro Devices Logo 




Gesamt 25 Seiten
PALCE29MA16 Datasheet, Funktion
FINAL
COM’L: H-25
PALCE29MA16H-25
24-Pin EE CMOS Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s High-performance semicustom logic
replacement; Electrically Erasable (EE)
technology allows reprogrammability
s 16 bidirectional user-programmable I/O logic
macrocells for Combinatorial/Registered/
Latched operation
s Output Enable controlled by a pin or product
terms
s Varied product term distribution for increased
design flexibility
s Programmable clock selection with common
pin clock/latch enable (LE) or individual
product term clock/LE with LOW/HIGH clock/
LE polarity
GENERAL DESCRIPTION
The PALCE29MA16 is a high-speed, EE CMOS Pro-
grammable Array Logic (PAL) device designed for gen-
eral logic replacement in TTL or CMOS digital systems.
It offers high speed, low power consumption, high
BLOCK DIAGRAM
s Register/Latch Preload permits full logic
verification
s High speed (tPD = 25 ns, fMAX = 33 MHz and fMAX
internal = 50 MHz)
s Full-function AC and DC testing at the factory
for high programming and functional yields
and high reliability
s 24-pin 300 mil SKINNYDIP and 28-pin plastic
leaded chip carrier packages
s Extensive third-party software and programmer
support through FusionPLD partners
programming yield, fast programming, and excellent
reliability. PAL devices combine the flexibility of custom
logic with the off-the-shelf availability of standard
products, providing major advantages over other
CLK/LE
I/OF7
I/OF6
I/O7
I/O6
I/O 5
I/O 4
I/OF5
I/OF4
I/O
Logic
Macrocell
4
4
I/O
Logic
Macrocell
4
4
I/O
Logic
Macrocell
4
8
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
4
12
4
12
4
8
4
4
4
4
Programmable
AND Array
58x178
4
4
4
4
8
4
12
4
12
4
8
4
4
4
4
4
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
4
I 0 -I3 I/OE
I/OF0
I/OF1
I/O0
I/O1
I/O2
I/O3
I/OF2
I/OF3
08811G-1
Publication# 08811 Rev. G Amendment /0
Issue Date: June 1993
2-349






PALCE29MA16 Datasheet, Funktion
AMD
Table 1a. PALCE29MA16 I/O Logic Macrocell Architecture Selections
S3 I/O Cell
1 Output Cell
0 Input Cell
S2 Storage Element
1 Register
0 Latch
S1 Output Type
1 Combinatorial
0 Register/Latch
S0 Output Polarity
1 Active LOW
0 Active HIGH
S8 Feedback*
1 Register/Latch
0 I/O
*Applies to macrocells with single feedback only.
Table 1b. PALCE29MA16 I/O Logic Macrocell Clock Polarity and Output Enable Selections
S4 S5 Clock Edge/Latch Enable Level
1 1 CLK/LE pin positive-going edge, active-LOW LE*
1 0 CLK/LE pin negative-going edge, active-HIGH LE*
0 1 CLK/LE PT positive-going edge, active-LOW LE*
0 0 CLK/LE PT negative-going edge, active-HIGH LE*
S6 S7 Output Buffer Control
1 1 Pin-Controlled Three-State Enable
1 0 PT-Controlled Three-State Enable
0 1 Permanently Enabled (Output only)
0 0 Permanently Disabled (Input only)
Notes:
1 = Erased State (Charged or disconnected).
0 = Programmed State (Discharged or connected).
*Active-LOW LE means that data is stored when the LE pin is HIGH, and the latch
is transparent when the LE pin is LOW. Active-HIGH LE means the opposite.
2-354
PALCE29MA16H-25

6 Page









PALCE29MA16 pdf, datenblatt
AMD
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = 0°C to +75°C) . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
Min Max Unit
VOH Output HIGH Voltage
IOH = –2 mA
VIN = VIH or VIL
2.4
V
VCC = Min
VOL Output LOW Voltage
IOL = 8 mA
VIN = VIH or VIL
0.5
IOL = 4 mA
IOL = 20 µA
VCC = Min
0.33 V
0.1
VIH Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0 V
VIL Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8 V
IIH
IIL
IOZH
IOZL
Input HIGH Leakage Current
Input LOW Leakage Current
Off-State Output Leakage
Current HIGH
Off-State Output Leakage
Current LOW
VIN = 5.5 V, VCC = Max (Note 2)
VIN = 0 V, VCC = Max (Note 2)
VOUT = 5.5 V, VCC = Max
VIN = VIH or VIL (Note 2)
VOUT = 5.5 V, VCC = Max
VIN = VIH or VIL (Note 2)
10 µA
–10 µA
10 µA
–10 µA
ISC Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 3)
–30 –130 mA
ICC Supply Current
VIN = 0 V, Outputs Open (IOUT = 0 mA)
VCC = Max
100 mA
Notes:
1. These are absolute values with respect to device ground all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-360
PALCE29MA16H-25 (Com’l)

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