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RF1S40N10LESM Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer RF1S40N10LESM
Beschreibung 40A/ 100V/ 0.040 Ohm/ Logic Level N-Channel Power MOSFETs
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 8 Seiten
RF1S40N10LESM Datasheet, Funktion
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Data Sheet
October 1999 File Number 4061.5
40A, 100V, 0.040 Ohm, Logic Level
N-Channel Power MOSFETs
These N-Channel enhancement mode power MOSFETs are
manufactured using the latest manufacturing process
technology. This process, which uses feature sizes
approaching those of LSI integrated circuits gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers and
relay drivers. These transistors can be operated directly from
integrated circuits.
Formerly developmental type TA49163.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFG40N10LE
TO-247
FG40N10L
RFP40N10LE
TO-220AB
FP40N10L
RF1S40N10LESM TO-263AB
F40N10LE
NOTE: When ordering, use the entire part number. Add the suffix, 9A, to
obtain the TO-263AB variant in tape and reel, i.e. RF1S40N10LESM9A.
Packaging
DRAIN
(FLANGE)
JEDEC STYLE TO-247
SOURCE
DRAIN
GATE
Features
• 40A, 100V
• rDS(ON) = 0.040
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-220AB
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
JEDEC TO-263AB
GATE
SOURCE
DRAIN
(FLANGE)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999






RF1S40N10LESM Datasheet, Funktion
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Test Circuits and Waveforms (Continued)
VDS
VGS
VGS
RGS
RL
DUT
+
VDD
-
FIGURE 18. SWITCHING TIME TEST CIRCUIT
VGS
Ig(REF)
VDS
RL
DUT
+
VDD
-
FIGURE 20. GATE CHARGE TEST CIRCUIT
VDS
tON
td(ON)
tr
90%
tOFF
td(OFF)
tf
90%
10%
0
VGS
10%
0
50%
PULSE WIDTH
10%
90%
50%
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDD
VGS
VGS = 2V
0
Qg(TOT)
VDS
Qg(10) OR Qg(5)
VGS = 20V
VGS = 10V FOR
L2 DEVICES
VGS = 1V FOR
L2 DEVICES
Qg(TH)
VGS = 10V
VGS = 5V FOR
L2 DEVICES
Ig(REF)
0
FIGURE 21. GATE CHARGE WAVEFORMS
6

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