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REJ03F0023_M61140FP Schematic ( PDF Datasheet ) - Hitachi Semiconductor

Teilenummer REJ03F0023_M61140FP
Beschreibung TUNER SINGLE CHIP
Hersteller Hitachi Semiconductor
Logo Hitachi Semiconductor Logo 




Gesamt 29 Seiten
REJ03F0023_M61140FP Datasheet, Funktion
M61140FP
TUNER SINGLE CHIP
REJ03F0023-0120Z
Rev.1.2
Apr.16.2004
Description
The M61140FP is a semiconductor integrated circuit consisting of Tuner signal processing for NTSC color TV and
VCRs.
The circuit includes Mixer circuit in Tuning system, Oscillator circuit, PLL frequency synthesizer and VIF/SIF, which
permits a smaller tuner system.
Features
VIF/SIF
Inter carrier type for NTSC
Coil-less VCO
Adjustment free AFT
High-speed IF AGC
PLL
Low phase noise and High-speed lock-up
Built-in band switch driver (4 port)
I2C bus control
Available for both XO and external reference
Mixer/Oscillator
Built-in U&V Oscillator and mixer
Built-in IF Amplifier (Unbalanced Output)
Application
TV, VCR
Recommended Operating Conditions
Supply voltage range --- 4.75 to 5.25V
Recommended supply voltage --- 5.0V
Rev.1.2, Apr.16.2004, page 1 of 28






REJ03F0023_M61140FP Datasheet, Funktion
M61140FP
Pin No. Pin name
15 PUHF
Function
Band change drive terminal.
Output configuration is PNP
open collector. When band
selection bit PUHF is set "1",
current is output.
Circuit Diagram
24
47K
15
16 V BAND IN
VHF RF input terminal.
Input type is unbalance.
24
16
17 RF GND
18 MIX
FILTER 1
19 MIX
FILTER 2
RF (Mixer) GND terminal.
Mixer output terminal. The
output terminal is open collector
type, single-tuned filter is
connected. This pin is pull-up
through power supply in order
for voltage to be above 4.2V.
24
18
19
20 PVHFH
21 PVHFL
Band change drive terminal.
Output configuration is PNP
open collector. When band
selection bit PVHFL or PVHFH is
set "1", current is output.
28
20
21
2 .2 K
2 .2 K
200 20p
200 20p
4K
4K
47K
Rev.1.2, Apr.16.2004, page 6 of 28

6 Page









REJ03F0023_M61140FP pdf, datenblatt
M61140FP
(1) WRITE mode
The information of 5 bytes required for circuit operational chip address, control data and band SW data of 2 bytes
and divider data of 2 bytes. after the chip address input, 2 or 4 bytes can be received. Function bit is contained in the
first and the third data byte to distinguish between divider and 'control data/band SW data', with "0" going ahead of
divider data, and "1" going ahead of 'control data/band SWdata'.
The timing of Writing data for bus protocol Mode is shown in the figure below. Divider data uses 15 bits and is read
in at the rise of the eighth clock bit of the second byte divider data (DB2). Control data (CB1) and band SW-data
(BB) are each read in at the rise of their eighth clock bit.
Timing Chart
SDA
address
DB1
DB2
CB1 CB2
SCL
Read into latch
Read into latch
Read into latch
Write mode data format
Byte
Address Byte (CA)
Divider Byte1 (DB1)
Divider Byte2 (DB2)
Control Byte (CB1)
Band Byte (CB2)
MSB
LSB
1
1
0
0
0
MA1
MA0
R/W=0 A
0 N14 N13 N12 N11 N10 N9 N8 A
N7 N6 N5 N4 N3 N2 N1 N0 A
1
CP T2
T1
T0
Rsa Rsb OS
A
X X X X PUHF PFMST PVHFH PVHFL A
Programmable Address Bit
Address input voltage applied to ADS [V]
0 to 0.1xVcc
Open or 0.2 to 0.3xVcc
0.4xVcc to 0.6xVcc
0.9xVcc to Vcc
MA1
0
0
1
1
MA0
0
1
0
1
N14 to N0 : Set up for division ratio of the programmable divider
Frequency of VCO fvco: fvco=fref x N
Division ratio N: N=N14(2^14 )+N13(2^13 )+ --- +N0(2^0)
Range of division ratio N: N=1,024 to 32,767
fref: Reference frequency of phase comparator
CP: Set up the charge pump current
CP Charge pump current *
0 70µA
1 300µA
Note:* Current of charge pump is typ current
In the case of setting current 270µA,when PLL is locked, charge pump current is automatically switched to CP=O
(70µA).
Rev.1.2, Apr.16.2004, page 12 of 28

12 Page





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