PALCE20V8H-5PI Datasheet PDF - Advanced Micro Devices
| Part Number | PALCE20V8H-5PI | |
| Description | EE CMOS 24-Pin Universal Programmable Array Logic | |
| Manufacturers | Advanced Micro Devices | |
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FINAL
COM’L: H-5/7/10/15/25, Q-10/15/25
IND: H-15/25, Q-20/25
PALCE20V8 Family
EE CMOS 24-Pin Universal Programmable Array Logic
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
s Pin and function compatible with all GAL
20V8/As
s Electrically erasable CMOS technology pro-
vides reconfigurable logic and full testability
s High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
s Direct plug-in replacement for a wide range of
24-pin PAL devices
s Programmable enable/disable control
s Outputs individually programmable as
registered or combinatorial
GENERAL DESCRIPTION
The PALCE20V8 is an advanced PAL device built with
low-power, high-speed, electrically-erasable CMOS
technology. Its macrocells provide a universal device
architecture. The PALCE20V8 is fully compatible with
the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.
Device logic is automatically configured according to the
user’s design specification. A design is implemented
using any of a number of popular design software pack-
ages, allowing automatic creation of a programming file
based on Boolean or state equations. Design software
also verifies the design and can provide test vectors for
the finished device. Programming can be accomplished
on standard PAL device programmers.
The PALCE20V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
BLOCK DIAGRAM
s Peripheral Component Interconnect (PCI)
compliant
s Preloadable output registers for testability
s Automatic register reset on power-up
s Cost-effective 24-pin plastic SKINNYDIP and
28-pin PLCC packages
s Extensive third-party software and programmer
support through FusionPLD partners
s Fully tested for 100% programming and func-
tional yields and high reliability
s Programmable output polarity
s 5-ns version utilizes a split leadframe for
improved performance
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equa-
tions are programmed into the device through floating-
gate cells in the AND logic array that can be erased
electrically.
The fixed OR array allows up to eight data product terms
per output for logic functions. The sum of these products
feeds the output macrocell. Each macrocell can be
programmed as registered or combinatorial with an
active-high or active-low output. The output configura-
tion is determined by two global bits and one local bit
controlling four multiplexers in each macrocell.
I1 – I10
10
CLK/I0
Programmable AND Array
40 x 64
Input
Mux.
MACRO
MC0
MACRO
MC1
MACRO
MC2
MACRO
MC3
MACRO
MC4
MACRO
MC5
MACRO
MC6
MACRO
MC7
Input
Mux.
OE/I11 I12 I/O0 I/O1 I/O2 I/O4 I/O4 I/O5 I/O6 I/O7 I13
Publication# 16491 Rev. D Amendment /0
Issue Date: February 1996
16491D-1
2-155
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Configuration Options
Each macrocell can be configured as one of the follow-
ing: registered output, combinatorial output, combinato-
rial I/O or dedicated input. In the registered output
configuration, the output buffer is enabled by the OE pin.
In the combinatorial configuration, the buffer is either
controlled by a product term or always enabled. In the
dedicated input configuration, the buffer is always dis-
abled. A macrocell configured as a dedicated input de-
rives the input signal from an adjacent I/O.
The macrocell configurations are controlled by the con-
figuration control word. It contains 2 global bits (SG0
and SG1) and 16 local bits (SL00 through SL07 and SL10
through SL17). SG0 determines whether registers will
be allowed. SG1 determines whether the PALCE20V8
will emulate a PAL20R8 family or a combinatorial de-
vice. Within each macrocell, SL0x, in conjunction with
SG1, selects the configuration of the macrocell and
SL1x sets the output as either active low or active high.
The configuration bits work by acting as control inputs
for the multiplexers in the macrocell. There are four mul-
tiplexers: a product term input, an enable select, an out-
put select, and a feedback select multiplexer. SG1 and
SL0x are the control signals for all four multiplexers. In
MC0 and MC7, SG0 replaces SG1 on the feedback
multiplexer.
These configurations are summarized in table 1 and il-
lustrated in figure 2.
If the PALCE20V8 is configured as a combinatorial de-
vice, the CLK and OE pins may be available as inputs to
the array. If the device is configured with registers, the
CLK and OE pins cannot be used as data inputs.
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0x =
0. There is only one registered configuration. All eight
product terms are available as inputs to the OR gate.
Data polarity is determined by SL1x. SL1x is an input to
the exclusive-OR gate which is the D input to the flip-
flop. SL1x is programmed as 1 for inverted output or 0
for non-inverted output. The flip-flop is loaded on the
LOW-to-HIGH transition of CLK. The feedback path is
from Q on the register. The output buffer is enabled by
OE.
Combinatorial Configurations
The PALCE20V8 has three combinatorial output con-
figurations: dedicated output in a non-registered device,
I/O in a non-registered device and I/O in a registered
device.
AMD
Dedicated Output in a Non-Registered
Device
The control settings are SG0 = 1, SG1 = 0, and SL0x = 0.
All eight product terms are available to the OR gate. Al-
though the macrocell is a dedicated output, the feed-
back is used, with the exception of pins 18(21) and
19(23). Pins 18(21) and 19(23) do not use feedback in
this mode.
Dedicated Input in a Non-Registered
Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0x =
1. The output buffer is disabled. The feedback signal is
an adjacent I/O pin.
Combinatorial I/O in a Non-Registered
Device
The control settings are SG0 = 1, SG1 = 1, and SL0x = 1.
Only seven product terms are available to the OR gate.
The eighth product term is used to enable the output
buffer. The signal at the I/O pin is fed back to the AND
array via the feedback multiplexer. This allows the pin to
be used as an input.
Combinatorial I/O in a Registered Device
The control bit settings are SG0=0,SG1=1 and SL0x =1.
Only seven product terms are available to the OR gate.
The eighth product term is used as the output enable.
The feedback signal is the corresponding I/O signal.
Table 1. Macrocell Configurations
SG0 SG1 SL0x Cell Configuration Devices Emulated
Device has registers
01
01
0 Registered
PAL20R8, 20R6,
Output
20R4
1 Combinatorial I/O PAL20R6, 20R4
10
10
11
Device has no registers
0 Combinatorial
PAL20L2,
Output
18L4,16L6,14L8
1 Dedicated Input PAL20L2,18L4,
16L6
1 Combinatorial I/O PAL20L8
Programmable Output Polarity
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.
Selection is made through a programmable bit SL1x
which controls an exclusive-OR gate at the output of the
AND/OR logic. The output is active high if SL1x is a 0
and active low if SL1x is a 1.
PALCE20V8 Family
2-159
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