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Teilenummer | PALCE20V8-25JI |
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Beschreibung | Flash Erasable/ Reprogrammable CMOS PAL Device | |
Hersteller | Cypress Semiconductor | |
Logo | ||
Gesamt 14 Seiten 20V8
PALCE20V8
Flash Erasable,
Reprogrammable CMOS PAL Device
Features
• Active pull-up on data input pins
• Low power version (20V8L)
— 55 mA max. commercial (15, 25 ns)
— 65 mA max. military/industrial
(15, 25 ns)
• Standard version has low power
— 90 mA max. commercial
(15, 25 ns)
— 115 mA max. commercial (10 ns)
— 130 mA max. military/industrial (15, 25 ns)
• CMOS Flash technology for electrical erasability and
reprogrammability
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combinato-
rial operation
• QSOP package available
— 10, 15, and 25 ns com’l version
— 15, and 25 ns military/industrial versions
• High reliability
— Proven Flash technology
— 100% programming and functional testing
Functional Description
The Cypress PALCE20V8 is a CMOS Flash Erasable sec-
ond-generation programmable array logic device. It is imple-
mented with the familiar sum-of-product (AND-OR) logic struc-
ture and the programmable macrocell.
The PALCE20V8 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerdip, a 28-lead square ceramic leadless chip car-
rier, a 28-lead square plastic leaded chip carrier, and a 24-lead
quarter size outline. The device provides up to 20 inputs and
8 outputs. The PALCE20V8 can be electrically erased and re-
programmed. The programmable macrocell enables the de-
vice to function as a superset to the familiar 24-pin PLDs such
as 20L8, 20R8, 20R6, 20R4.
Logic Block Diagram (PDIP/CDIP/QSOP)
GND
12
I10
11
I9
10
I8 I7 I6
9 87
I5 I4
65
I3 I2 I1 CLK/I0
4 3 21
PROGRAMMABLE
AND ARRAY
(64 x 40)
8 8 8 88 8 8
8
MUX
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
MUX
13 14
15
16
17
18
OE/I11
I12
I/O0
I/O1
I/O2
I/O3
PAL is a registered trademark of Advanced Micro Devices, Inc.
19
I/O4
20 21 22 23 24
I/O5 I/O6 I/O7 I13 VCC
20V8–1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-03026 Rev. **
Revised March 26, 1997
PALCE20V8
Commercial and Industrial Switching Characteristics[2]
20V8−5
20V8−7
20V8−10
20V8−15
20V8−25
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tPD
Input to Output
Propagation Delay[8]
1 5 1 7.5 1 10 1 15 1 25 ns
tPZX OE to Output Enable
tPXZ OE to Output Disable
tEA
Input to Output
Enable Delay[7]
5 6 10 15 20 ns
5 6 10 15 20 ns
6 9 10 15 25 ns
tER
Input to Output
Disable Delay[7,9]
6 9 10 15 25 ns
tCO
Clock to Output Delay[8]
1 4 1 5 1 7 1 10 1 12 ns
tS Input or Feedback
Set-Up Time
3 7 10 12 15 ns
tH Input Hold Time
0 0 0 0 0 ns
tP External Clock Period
(tCO + tS)
tWH Clock Width HIGH[7]
tWL Clock Width LOW[7]
7
3
3
12 17 22 27 ns
5 8 8 12 ns
5 8 8 12 ns
fMAX1
External Maximum
Frequency (1/(tCO + tS))[7,10]
143
83
58 45.5 37 MHz
fMAX2
Data Path Maximum
166.
100
62.5
62.5
41.6 MHz
Frequency
6
(1/(tWH + tWL))[7, 11]
fMAX3
Internal Feedback Maximum 166.
Frequency (1/(tCF + tS))[7,12]
6
100
62.5
50
40 MHz
tCF
Register Clock to
Feedback Input[7, 13]
3 3 6 8 10 ns
tPR
Power-Up Reset Time[7]
1
1
1
1
1 µs
Shaded area contains preliminary information.
Notes:
8. Min. times are tested initially and after any design or process changes that may affect these parameters.
9. This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous
HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max.
10. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
11. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
12. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
13. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note 7 above) minus tS.
Document #: 38-03026 Rev. **
Page 6 of 14
6 Page Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL−STD−1835 D−9 Config.A
PALCE20V8
28-Lead Plastic Leaded Chip Carrier J64
28-Square Leadless Chip Carrier L64
MIL−STD−1835 C−4
Document #: 38-03026 Rev. **
Page 12 of 14
12 Page | ||
Seiten | Gesamt 14 Seiten | |
PDF Download | [ PALCE20V8-25JI Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
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