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RFP10P03L Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer RFP10P03L
Beschreibung 10A/ 30V/ 0.200 Ohm/ Logic Level/ P-Channel Power MOSFET
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 8 Seiten
RFP10P03L Datasheet, Funktion
RFD10P03L, RFD10P03LSM, RFP10P03L
Data Sheet
July 1999 File Number 3515.2
10A, 30V, 0.200 Ohm, Logic Level,
P-Channel Power MOSFET
These products are P-Channel power MOSFETs
manufactured using the MegaFET process. This process,
which uses feature sizes approaching those of LSI circuits,
gives optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, and relay drivers. These transistors can be operated
directly from integrated circuits.
Formerly developmental type TA49205.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFD10P03L
TO-251AA
10P03L
RFD10P03LSM
TO-252AA
10P03L
RFP10P03L
TO-220AB
F10P03L
NOTE: When ordering, use the entire part number. Add the suffix, 9A,
to obtain the TO-252AA variant in tape and reel, i.e. RFD10P03LSM9A..
Packaging
JEDEC TO-251AA
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
Features
• 10A, 30V
• rDS(ON) = 0.200
• Temperature Compensating PSPICE® Model
• PSPICE Thermal Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
Symbol
D
G
S
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
JEDEC TO-220AB
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
7-3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999






RFP10P03L Datasheet, Funktion
RFD10P03L, RFD10P03LSM, RFP10P03L
Test Circuits and Waveforms (Continued)
VGS
DUT
RG
RL
-
VDD
+
FIGURE 18. SWITCHING TIME TEST CIRCUIT
tON
td(ON)
tr
0
10%
tOFF
td(OFF)
tf
10%
VDS
VGS
0
90%
10%
50%
PULSE WIDTH
90%
50%
90%
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VGS
IG(REF)
VDS
RL
DUT
-
VDD
+
FIGURE 20. GATE CHARGE TEST CIRCUIT
0
VGS= -1V
-VGS
VDD
0
Ig(REF)
Qg(TH)
VDS
Qg(-5)
VGS= -5V
Qg(TOT)
VGS= -10V
FIGURE 21. GATE CHARGE WAVEFORMS
7-8

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