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PDF RFD7N10LE Data sheet ( Hoja de datos )
| Número de pieza | RFD7N10LE | |
| Descripción | 7A/ 100V/ 0.300 Ohm/ N-Channel/ Logic Level/ Power MOSFETs | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
RFD7N10LE, RFD7N10LESM
October 1999 File Number 3598.3
7A, 100V, 0.300 Ohm, N-Channel, Logic
Level, Power MOSFETs
These N-Channel power MOSFETs are manufactured using
a modern process. This process, which uses feature sizes
approaching those of LSI integrated circuits gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers,
relay drivers and emitter switches for bipolar transistors. This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate bias in
the 3V to 5V range, thereby facilitating true on-off power
control directly from logic level (5V) integrated circuits.
Formerly developmental type TA49046.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFD7N10LE
TO-251AA
7N10L
RFD7N10LESM
TO-252AA
7N10LE
NOTE: When ordering, use the entire part number. Add suffix 9A to ob-
tain the TO-252AA variant in the tape and reel, i.e., RFD7N10LESM9A.
Features
• 7A, 100V
• rDS(ON) = 0.300Ω
• Temperature Compensating PSPICE® Model
• Can be Driven Directly from CMOS, NMOS, TTL Circuits
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
Packaging
JEDEC TO-251AA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
JEDEC TO-252AA
DRAIN
(FLANGE)
GATE
SOURCE
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
RFD7N10LE, RFD7N10LESM
Typical Performance Curves Unless Otherwise Specified (Continued)
600
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
CISS
400
200
0
0
COSS
CRSS
5 10 15 20
VDS, DRAIN TO SOURCE VOLTAGE (V)
25
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
100
VDD = BVDSS
75
VDD = BVDSS
5.00
3.75
50 0.75 BVDSS 0.75 BVDSS
0.50 BVDSS 0.50 BVDSS
0.25 BVDSS 0.25 BVDSS
25 RL = 14.28Ω
IG(REF) = 0.24mA
VGS = 5V
0
20 I-I-GG-----((--AR----CE----FT----))
t, TIME (µs)
80 I-I-GG-----((--AR----CE----FT----))
2.50
1.25
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
L
DUT
+
VDD
-
IAS
0.01Ω
0
tP
IAS
BVDSS
VDS
VDD
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
VDS
VGS
VGS
RGS
RL
DUT
+
VDD
-
FIGURE 16. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS
tON
td(ON)
tr
90%
tOFF
td(OFF)
tf
90%
10%
0
VGS
10%
0
50%
PULSE WIDTH
10%
90%
50%
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet RFD7N10LE.PDF ] | |
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| RFD7N10LE | 7A/ 100V/ 0.300 Ohm/ N-Channel/ Logic Level/ Power MOSFETs | Intersil Corporation |
| RFD7N10LESM | 7A/ 100V/ 0.300 Ohm/ N-Channel/ Logic Level/ Power MOSFETs | Intersil Corporation |
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