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RFD3N08L Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer RFD3N08L
Beschreibung 3A/ 80V/ 0.800 Ohm/ Logic Level/ N-Channel Power MOSFETs
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 8 Seiten
RFD3N08L Datasheet, Funktion
Data Sheet
RFD3N08L, RFD3N08LSM
July 1999 File Number 2836.4
3A, 80V, 0.800 Ohm, Logic Level,
N-Channel Power MOSFETs
The RFD3N08L and RFD3N08LSM are N-Channel
enhancement mode silicon gate power field effect transistors
specifically designed for use with logic level (5V) driving
sources in applications such as programmable controllers,
automotive switching, and solenoid drivers. This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate biases
in the 3V to 5V range, thereby facilitating true on-off power
control directly from logic circuit supply voltages.
Formerly developmental type TA09922.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFD3N08L
TO-251AA
F3N08L
RFD3N08LSM
TO-252AA
F3N08L
NOTE: When ordering, include the entire part number. Add the suffix 9A
to obtain the TO-252AA variant in tape and reel, i.e. RFD3N08LSM9A
Packaging
JEDEC TO-251AA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
Features
• 3A, 80V
• rDS(ON) = 0.800
• Temperature Compensating PSPICE® Model
• On Resistance vs Gate Drive Voltage Curves
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-252AA
DRAIN
(FLANGE)
GATE
SOURCE
6-26
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999






RFD3N08L Datasheet, Funktion
RFD3N08L, RFD3N08LSM
Test Circuits and Waveforms (Continued)
RL
+
RG
VDD
-
DUT
VGS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
VGS
Ig(REF)
VDS
RL
DUT
+
VDD
-
FIGURE 20. GATE CHARGE TEST CIRCUIT
VDS
tON
td(ON)
tr
90%
tOFF
td(OFF)
tf
90%
10%
0
VGS
10%
0
50%
PULSE WIDTH
10%
90%
50%
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDD
VDS
Qg(TOT)
VGS
VGS = 1V
0
IG(REF)
0
Qg(5)
Qg(TH)
VGS = 5V
VGS = 10V
FIGURE 21. GATE CHARGE WAVEFORMS
6-31

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