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PDF RFD15N06LE Data sheet ( Hoja de datos )

Número de pieza RFD15N06LE
Descripción 15A/ 60V/ 0.065 Ohm/ ESD Rated/ Logic Level/ N-Channel Power MOSFETs
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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Data Sheet
RFD15N06LE, RFD15N06LESM
April 1999 File Number 4079.1
15A, 60V, 0.065 Ohm, ESD Rated, Logic
Level, N-Channel Power MOSFETs
These are N-Channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI circuits, gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers,
and relay drivers. These transistors can be operated directly
from integrated circuits.
Formerly developmental type TA49165.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFD15N06LE
TO-251AA
F15N6L
RFD15N06LESM TO-252AA
F15N6L
NOTE: When ordering, use the entire part number. For ordering in tape
and reel, add the suffix 9A to the part number, i.e. RFD15N06LESM9A.
Features
• 15A, 60V
• rDS(ON) = 0.065
• 2kV ESD Protected
• Temperature Compensating PSPICE™ Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
Packaging
JEDEC TO-251AA
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
6-149
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE™ is a trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

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RFD15N06LE pdf
RFD15N06LE, RFD15N06LESM
Typical Performance Curves Unless Otherwise Specified (Continued)
1.2 1.2
VGS = VDS, ID = 250µA
ID = 250µA
1.0 1.1
0.8 1.0
0.6 0.9
0.4
-80
-40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
1200
1000
800
600
400
200
0
0
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGD
CISS
COSS
CRSS
5 10 15 20
VDS, DRAIN TO SOURCE VOLTAGE (V)
25
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
RG
tP
0V
VDS
L
DUT
+
VDD
-
IAS
0.01
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
6-153
0.8
-80
-40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
60 5.00
VDD = BVDSS
VDD = BVDSS
45 3.75
RL =4.00
IG(REF) = 0.44mA
VGS = 5V
30 2.50
PLATEAU VOLTAGES IN
DESCENDING ORDER:
15 VDD = BVDSS
1.25
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
00
20 I-I-G-G-----((--AR-----CE----F-T---)-)
t, TIME (ms)
80 I-I-G-G-----((--AR-----CE----F-T---)-)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS

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