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RFD14N05L Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer RFD14N05L
Beschreibung 14A/ 50V/ 0.100 Ohm/ Logic Level/ N-Channel Power MOSFETs
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 8 Seiten
RFD14N05L Datasheet, Funktion
RFD14N05L, RFD14N05LSM, RFP14N05L
Data Sheet
January 2002
14A, 50V, 0.100 Ohm, Logic Level,
N-Channel Power MOSFETs
These are N-channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relay drivers. This performance is accomplished
through a special gate oxide design which provides full rated
conductance at gate bias in the 3V-5V range, thereby
facilitating true on-off power control directly from logic level
(5V) integrated circuits.
Formerly developmental type TA09870.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFD14N05L
TO-251AA
14N05L
RFD14N05LSM
TO-252AA
14N05L
RFP14N05L
TO-220AB
FP14N05L
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-252AA variant in the tape and reel, i.e., RFD14N05LSM9A.
Features
• 14A, 50V
• rDS(ON) = 0.100
• Temperature Compensating PSPICE® Model
• Can be Driven Directly from CMOS, NMOS, and
TTL Circuits
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
Packaging
JEDEC TO-251AA
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
JEDEC TO-252AA
GATE
SOURCE
DRAIN (FLANGE)
JEDEC TO-220AB
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
©2002 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B






RFD14N05L Datasheet, Funktion
RFD14N05L, RFD14N05LSM, RFP14N05L
Test Circuits and Waveforms (Continued)
VDS
VGS
VGS
RGS
RL
DUT
+
VDD
-
FIGURE 18. SWITCHING TIME TEST CIRCUIT
VGS
IG(REF)
VDS
RL
DUT
+
VDD
-
FIGURE 20. GATE CHARGE TEST CIRCUIT
VDS
tON
td(ON)
tr
90%
tOFF
td(OFF)
tf
90%
10%
0
VGS
10%
0
50%
PULSE WIDTH
10%
90%
50%
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDD
VDS
Qg(TOT)
VGS
VGS = 1V
0
IG(REF)
0
Qg(5)
Qg(TH)
VGS = 5V
VGS = 10V
FIGURE 21. GATE CHARGE WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B

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