Datenblatt-pdf.com


PALCE16V8 Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer PALCE16V8
Beschreibung EE CMOS 20-Pin Universal Programmable Array Logic
Hersteller Lattice Semiconductor
Logo Lattice Semiconductor Logo 




Gesamt 30 Seiten
PALCE16V8 Datasheet, Funktion
PALCE16V8 COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25
PALCE16V8Z COM’L:-25
IND:-12/15/25
PALCE16V8 and PALCE16V8Z Families
EE CMOS (Zero-Power) 20-Pin Universal
Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
x Pin and function compatible with all 20-pin PAL® devices
x Electrically erasable CMOS technology provides reconfigurable logic and full testability
x High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
x Direct plug-in replacement for the PAL16R8 series
x Outputs programmable as registered or combinatorial in any combination
x Peripheral Component Interconnect (PCI) compliant
x Programmable output polarity
x Programmable enable/disable control
x Preloadable output registers for testability
x Automatic register reset on power up
x Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
x Extensive third-party software and programmer support
x Fully tested for 100% programming and functional yields and high reliability
x 5-ns version utilizes a split leadframe for improved performance
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-
erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The
macrocells provide a universal device architecture. The PALCE16V8 will directly replace the
PAL16R8, with the exception of the PAL16C1.
The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby
current, the PALCE16V8Z allows battery-powered operation for an extended period.
The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate
cells in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.
Publication# 16493 Rev: F
Amendment/0
Issue Date: September 2000






PALCE16V8 Datasheet, Funktion
OE
DQ
CLK Q
a. Registered active low
OE
DQ
CLK Q
b. Registered active high
c. Combinatorial I/O active low
VCC
d. Combinatorial I/O active high
VCC
Note 1
e. Combinatorial output active low
Note 1
f. Combinatorial output active high
Notes:
1. Feedback is not available on pins 15 and 16 in the
combinatorial output mode.
2. This configuration is not available on pins 15 and 16.
Adjacent I/O pin
Note 2
g. Dedicated input
Figure 2. Macrocell Configurations
16493E-2
6 PALCE16V8 and PALCE16V8Z Families

6 Page









PALCE16V8 pdf, datenblatt
CAPACITANCE1
Parameter
Symbol
Parameter Description
Test Conditions
Typ Unit
CIN Input Capacitance
COUT Output Capacitance
VIN = 2.0 V
VOUT = 2.0 V
VCC = 5.0 V, TA = 25 °C,
f = 1 MHz
5 pF
8 pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES1
Parameter
Symbol
Parameter Description
-5
Min 2 Max
-7
Min 2 Max
Unit
tPD
tS
tH
tCO
tSKEWR
tWL
tWH
fMAX
tPZX
tPXZ
tEA
tER
Input or Feedback to Combinatorial Output
Setup Time from Input or Feedback to Clock
Hold Time
Clock to Output
Skew Between Registered Outputs (Note 3)
Clock Width
LOW
HIGH
Maximum Frequency
(Note 4)
External Feedback
Internal Feedback (fCNT)
No Feedback
OE to Output Enable
OE to Output Disable
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
1/(tS+tCO)
1/(tS+tCF) (Note 5)
1/(tWH+tWL)
15
3
0
14
1
3
3
142.8
166
166
16
15
26
25
3 7.5 ns
5 ns
0 ns
1 5 ns
1 ns
4 ns
4 ns
100 MHz
125 MHz
125 MHz
1 6 ns
1 6 ns
3 9 ns
3 9 ns
Notes:
1. See “Switching Test Circuit” for test conditions.
2. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements
may alter these values; therefore, minimum values are recommended for simulation purposes only.
3. Skew testing takes into account pattern and switching direction differences between outputs that have equal loading.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
12 PALCE16V8H-5/7 (Com’l)

12 Page





SeitenGesamt 30 Seiten
PDF Download[ PALCE16V8 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
PALCE16V8EE CMOS 20-Pin Universal Programmable Array LogicLattice Semiconductor
Lattice Semiconductor
PALCE16V8Reprogrammable CMOS PAL DeviceCypress Semiconductor
Cypress Semiconductor
PALCE16V8EE CMOS 20-Pin Universal Programmable Array LogicAdvanced Micro Devices
Advanced Micro Devices
PALCE16V8H-15EE CMOS Universal Programmable Array LogicAdvanced Micro Devices
Advanced Micro Devices
PALCE16V8H-25EE CMOS Universal Programmable Array LogicAdvanced Micro Devices
Advanced Micro Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche