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RM5231-150-Q Schematic ( PDF Datasheet ) - PMC-Sierra Inc

Teilenummer RM5231-150-Q
Beschreibung RM5231 Microprocessor with 32-Bit System Bus Data Sheet Released
Hersteller PMC-Sierra Inc
Logo PMC-Sierra  Inc Logo 




Gesamt 30 Seiten
RM5231-150-Q Datasheet, Funktion
RM5231Microprocessor with 32-Bit System Bus Data Sheet
Released
RM5231
RM5231Microprocessor with 32-Bit
System Bus
Data Sheet
Proprietary and Confidential
Issue 1, March 2001
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers Internal Use
Document ID: PMC-2002165, Issue 1






RM5231-150-Q Datasheet, Funktion
RM5231Microprocessor with 32-Bit System Bus Data Sheet
Released
3.31 Boot-Time Options .......................................................................................................24
3.32 Boot-Time Modes .........................................................................................................25
4 Pin Descriptions ....................................................................................................................26
5 Absolute Maximum Ratings ..................................................................................................29
6 Recommended Operating Conditions ...................................................................................30
7 DC Electrical Characteristics .................................................................................................31
8 Power Consumption ..............................................................................................................32
9 AC Electrical Characteristics .................................................................................................33
9.1 Capacitive Load Deration .............................................................................................33
9.2 Clock Parameters ........................................................................................................33
9.3 System Interface Parameters .......................................................................................34
9.4 Boot-Time Interface Parameters ..................................................................................34
10 Timing Diagrams ...................................................................................................................35
10.1 System Interface Timing ..............................................................................................35
11 Packaging Information ..........................................................................................................36
12 RM5231 128-pin PQFP Package Pinout ...............................................................................38
13 Ordering Information .............................................................................................................39
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers Internal Use
Document ID: PMC-2002165, Issue 1
6

6 Page









RM5231-150-Q pdf, datenblatt
RM5231Microprocessor with 32-bit System Bus Data Sheet
Released
Figure 3 Pipeline
I0 1I 2I 1R 2R 1A 2A 1D 2D 1W 2W
I1 1I 2I 1R 2R 1A 2A 1D 2D 1W 2W
I2 1I 2I 1R 2R 1A 2A 1D 2D 1W 2W
I3 1I 2I 1R 2R 1A 2A 1D 2D 1W 2W
I4 1I 2I 1R 2R 1A 2A 1D 2D 1W 2W
one cycle
1I-1R: Instruction cache access
2I: Instruction virtual to physical address translation
2R: Register file read, Bypass calculation, Instruction decode, Branch address calculation
1A: Issue or slip decision, Branch decision
1A: Data virtual address calculation
1A-2A: Integer add, logical, shift
2A: Store Align
2A-2D: Data cache access and load align
1D: Data virtual to physical address translation
2W: Register file write
3.4 Integer Unit
The RM5231 integer unit includes thirty-two general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous
multiply/divide unit. Additional register resources include: the HI/LO result registers for the two-
operand integer multiply/divide operations, and the program counter (PC).
The RM5231 implements the MIPS IV Instruction Set Architecture, and is therefore fully upward
compatible with applications that run on processors implementing the earlier generation MIPS I-
III instruction sets.
3.5 Register File
The RM5231 has thirty-two general purpose registers with register location 0 (r0) hard wired to a
zero value. These registers are used for scalar integer operations and address calculation. The
register file has two read ports and one write port and is fully bypassed to minimize operation
latency in the pipeline.
3.6 ALU
The RM5231 ALU consists of an integer adder/subtractor, a logic unit, and a shifter. The adder
performs address calculations in addition to arithmetic operations. The logic unit performs all
logical and zero shift data moves. The shifter performs shifts and store alignment operations. Each
of these units is optimized to perform all operations in a single processor cycle.
3.7 Integer Multiply/Divide
The RM5231 has a dedicated integer multiply/divide unit optimized for high-speed multiply and
multiply-accumulate operations. Table 1 shows the performance of the multiply/divide unit on
each operation.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers Internal Use
Document ID: PMC-2002165, Issue 1
12

12 Page





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