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RLP03N06CLE Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer RLP03N06CLE
Beschreibung 0.3A/ 60V/ 6 Ohm/ ESD Rated/ Current Limited/ Voltage Clamped/ Logic Level N-Channel Power MOSFETs
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 9 Seiten
RLP03N06CLE Datasheet, Funktion
Data Sheet
RLD03N06CLE, RLD03N06CLESM,
RLP03N06CLE
July 1999 File Number 3948.5
0.3A, 60V, 6 Ohm, ESD Rated, Current
Limited, Voltage Clamped, Logic Level
N-Channel Power MOSFETs
These are intelligent monolithic power circuits which
incorporate a lateral bipolar transistor, resistors, zener
diodes and a power MOS transistor. The current limiting of
these devices allow it to be used safely in circuits where a
shorted load condition may be encountered. The drain to
source voltage clamping offers precision control of the circuit
voltage when switching inductive loads. The “Logic Level”
gate allows this device to be fully biased on with only 5V
from gate to source, thereby facilitating true on-off power
control directly from logic level (5V) integrated circuits.
These devices incorporate ESD protection and are designed
to withstand 2kV (Human Body Model) of ESD.
Formerly developmental type TA49028.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RLD03N06CLE
TO-251AA
03N06C
RLD03N06CLESM TO-252AA
03N06C
RLP03N06CLE
TO-220AB
03N06CLE
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-252AA variant in tape and reel, i.e. RLD03N06CLESM9A.
Packaging
JEDEC TO-251AA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
Features
• 0.30A, 60V
• rDS(ON) = 6.0
• Built in Current Limit ILIMIT 0.140 to 0.210A at 150oC
• Built in Voltage Clamp
• Temperature Compensating PSPICE® Model
• 2kV ESD Protected
• Controlled Switching Limits EMI and RFI
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-252AA
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
JEDEC TO-220AB
SOURCE
DRAIN
GATE
6-418
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999






RLP03N06CLE Datasheet, Funktion
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
The results of this equation are plotted in Figure 15 for various
heatsinks.
Duty Cycle Operation
In many applications either the drain to source voltage or the
gate drive is not available 100% of the time. The copper header
on which the RLD03N06CLE, CLESM and RLP03N06CLE is
mounted has a very large thermal storage capability, so for
pulse widths of less then 1ms, the temperature of the header
can be considered a constant, thereby the junction temperature
can be calculated simply as shown in Equation 2:
TC = (VDS ID D RθCA) + TAMBIENT
(EQ. 2)
Generally the heat storage capability of the silicon chip in a
power transistor is ignored for duty cycle calculations. Making
this assumption, limiting junction temperature to 175oC and
using the TC calculated in Equation 2, the expression for ma-
ximum VDS under duty cycle operation is shown in Equation 3
o:
VDS = I--L----1M---5---0-----D---C-----–--R---T--θ--C-J----C--
(EQ. 3)
Typical Performance Curves
90
75
HSTR = 5oC/W
60
HSTR = 10oC/W
45
HSTR = 0oC/W
HSTR = 1oC/W
HSTR = 2oC/W
TJ = 175oC
IRLθIMJC==0.52.100oAC/W
30 HSTR = 25oC/W
15 HSTR = 80oC/W
0
25 50 75 100 125 150 175
TA , AMBIENT TEMPERATURE (oC)
NOTE: Heat Sink Thermal Resistance = HSTR.
FIGURE 15. DC OPERATION IN CURRENT LIMITING
90
75
DC = 50%
60
DC = 2%
DC = 20%
DC = 5%
DC = 10%
45
30 TJ = 175oC
15 IRLθIMJC==0.52.100oAC/W
DUTY CYCLE = DC MAX PULSE WIDTH = 100ms
0
100 125 150
TA , AMBIENT TEMPERATURE (oC)
175
FIGURE 17.
MAXIMUM
CURRENT
VLIDMSITvIsNAGM. B(HIESNTTRT=E2MoPCE/WR)ATURE
IN
These values are plotted as Figures 16 through 21 for vari-
ous heatsink thermal resistances.
Limited Time Operations
Protection for a limited period of time is sufficient for many
applications. As stated above the heat storage in the silicon
chip can usually be ignored for computations of over 10 ms,
thereby the thermal equivalent circuit reduces to a simple
enough circuit to allow easy computation on the limiting
conditions. The variation in limiting current with temperature
complicates the calculation of junction temperature, but a
simple straight line approximation of the variation is accurate
enough to allow meaningful computations. The curves shown
as Figures 22 through 25 (RLP03N06CLE) and Figure 26
through 29 (RLD03N06CLE and RLD03N06CLESM) give an
accurate indication of how long the specified voltage can be
applied to the device in the current limiting mode without
exceeding the maximum specified 175oC junction temperature.
In practice this tells you how long you have to alleviate the
condition causing the current limiting to occur.
90
DC = 50%
75
60
45
DC = 20%
DC = 2%
DC = 5%
DC = 10%
30
TJ = 175oC
15 RILθIMJC==0.52.100oAC/W
DUTY CYCLE = DC MAX PULSE WIDTH = 100ms
0
100 125 150 175
TA , AMBIENT TEMPERATURE (oC)
FIGURE 16. MAXIMUM VDS vs AMBIENT TEMPERATURE IN
CURRENT LIMITING. (HEATSINK THERMAL
RESISTANCE = 1oC/W)
90
75
DC = 20%
DC = 2%
DC = 5%
60
DC = 50%
45
DC = 10%
30
TJ = 175oC
15 IRLθIMJC==0.52.100oAC/W
DUTY CYCLE = DC MAX PULSE WIDTH = 100ms
0
75 100 125 150
TA , AMBIENT TEMPERATURE (oC)
175
FIGURE 18.
MAXIMUM
CURRENT
VLIDMSITvIsNAGM. B(HIESNTTRT=E5MoPCE/WR)ATURE
IN
6-423

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