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PA28F400BVB80 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer PA28F400BVB80
Beschreibung 4-MBIT (256K X 16/ 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 57 Seiten
PA28F400BVB80 Datasheet, Funktion
E
PRELIMINARY
4-MBIT (256K X 16, 512K X 8)
SmartVoltage BOOT BLOCK FLASH
MEMORY FAMILY
28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B
28F400CE-T/B, 28F004BE-T/B
n Intel SmartVoltage Technology
5V or 12V Program/Erase
2.7V, 3.3V or 5V Read Operation
Increased Programming Throughput
at 12V VPP
n Very High-Performance Read
5V: 60/80/120 ns Max. Access Time,
30/40 ns Max. Output Enable Time
3V: 110/150/180 ns Max Access
65/90 ns Max. Output Enable Time
2.7V: 120 ns Max Access 65 ns Max.
Output Enable Time
n Low Power Consumption
Max 60 mA Read Current at 5V
Max 30 mA Read Current at
2.7V–3.6V
n x8/x16-Selectable Input/Output Bus
28F400 for High Performance 16- or
32-bit CPUs
n x8-Only Input/Output Architecture
28F004B for Space-Constrained
8-bit Applications
n Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
Three 128-KB Main Blocks
Top or Bottom Boot Locations
n Absolute Hardware-Protection for Boot
Block
n Software EEPROM Emulation with
Parameter Blocks
n Extended Temperature Operation
–40°C to +85°C
n Extended Cycling Capability
100,000 Block Erase Cycles
(Commercial Temperature)
10,000 Block Erase Cycles
(Extended Temperature)
n Automated Word/Byte Program and
Block Erase
Industry-Standard Command User
Interface
Status Registers
Erase Suspend Capability
n SRAM-Compatible Write Interface
n Automatic Power Savings Feature
1 mA Typical ICC Active Current in
Static Operation
n Reset/Deep Power-Down Input
0.2 µA ICCTypical
Provides Reset for Boot Operations
n Hardware Data Protection Feature
Write Lockout during Power
Transitions
n Industry-Standard Surface Mount
Packaging
40-Lead TSOP
44-Lead PSOP: JEDEC ROM
Compatible
48-Lead TSOP
56-Lead TSOP
n Footprint Upgradeable from 2-Mbit and
to 8-Mbit Boot Block Flash Memories
n ETOX™ IV Flash Technology
July 1997
Order Number: 290530-005






PA28F400BVB80 Datasheet, Funktion
4-MBIT SmartVoltage BOOT BLOCK FAMILY
E
For program and erase operations, 5V VPP
operation eliminates the need for in system voltage
converters, while 12V VPP operation provides faster
program and erase for situations where 12V is
available, such as manufacturing or designs where
12V is in-system. For design simplicity, however,
just hook up VCC and VPP to the same 5V ± 10%
source.
The 28F400/28F004B boot block flash memory
family is a high-performance, 4-Mbit (4,194,304 bit)
flash memory family organized as either
256 Kwords of 16 bits each (28F400 only) or
512 Kbytes of 8 bits each (28F400 and 28F004B).
Separately erasable blocks, including a hardware-
lockable boot block (16,384 bytes), two parameter
blocks (8,192 bytes each) and main blocks (one
block of 98,304 bytes and three blocks of 131,072
bytes), define the boot block flash family
architecture. See Figures 7 and 8 for memory
maps. Each block can be independently erased and
programmed 100,000 times at commercial
temperature or 10,000 times at extended
temperature.
The boot block is located at either the top (denoted
by -T suffix) or the bottom (-B suffix) of the address
map in order to accommodate different
microprocessor protocols for boot code location.
The hardware-lockable boot block provides
complete code security for the kernel code required
for system initialization. Locking and unlocking of
the boot block is controlled by WP# and/or RP#
(see Section 3.4 for details).
The Command User Interface (CUI) serves as the
interface between the microprocessor or
microcontroller and the internal operation of the
boot block flash memory products. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations, including verifications,
thereby unburdening the microprocessor or
microcontroller of these tasks. The Status Register
(SR) indicates the status of the WSM and whether it
successfully completed the desired program or
erase operation.
Program and Erase Automation allows program and
erase operations to be executed using an industry-
standard two-write command sequence to the CUI.
Data writes are performed in word (28F400 family)
or byte (28F400 or 28F004B families) increments.
Each byte or word in the flash memory can be
programmed independently of other memory
locations, unlike erases, which erase all locations
within a block simultaneously.
The 4-Mbit SmartVoltage boot block flash memory
family is also designed with an Automatic Power
Savings (APS) feature which minimizes system
battery current drain, allowing for very low power
designs. To provide even greater power savings,
the boot block family includes a deep power-down
mode which minimizes power consumption by
turning most of the flash memory’s circuitry off.
This mode is controlled by the RP# pin and its
usage is discussed in Section 3.5, along with other
power consumption issues.
Additionally, the RP# pin provides protection
against unwanted command writes due to invalid
system bus conditions that may occur during
system reset and power-up/down sequences. For
example, when the flash memory powers-up, it
automatically defaults to the read array mode, but
during a warm system reset, where power
continues uninterrupted to the system components,
the flash memory could remain in a non-read mode,
such as erase. Consequently, the system Reset
signal should be tied to RP# to reset the memory to
normal read mode upon activation of the Reset
signal. See Section 3.6.
The 28F400 provides both byte-wide or word-wide
input/output, which is controlled by the BYTE# pin.
Please see Table 2 and Figure 16 for a detailed
description of BYTE# operations, especially the
usage of the DQ15/A–1 pin.
The 28F400 products are available in a
ROM/EPROM-compatible pinout and housed in the
44-lead PSOP (Plastic Small Outline) package, the
48-lead TSOP (Thin Small Outline, 1.2 mm thick)
package and the 56-lead TSOP as shown in
Figures 4, 5 and 6, respectively. The 28F004
products are available in the 40-lead TSOP
package as shown in Figure 3.
Refer to the DC Characteristics Table, Section 5.2
(commercial temperature) and Section 6.2
(extended temperature), for complete current and
voltage specifications. Refer to the AC
Characteristics Table, Section 5.3 (commercial
temperature) and Section 6.3 (extended
temperature), for read, write and erase performance
specifications.
6 PRELIMINARY

6 Page









PA28F400BVB80 pdf, datenblatt
4-MBIT SmartVoltage BOOT BLOCK FAMILY
E
Symbol
WP#
BYTE#
VCC
VPP
GND
NC
Type
INPUT
INPUT
Table 2. 28F400/004 Pin Descriptions (Continued)
Name and Function
WRITE PROTECT: Provides a method for unlocking the boot block in a system
without a 12V supply.
When WP# is at logic low, the boot block is locked, preventing program and
erase operations to the boot block. If a program or erase operation is attempted
on the boot block when WP# is low, the corresponding status bit (bit 4 for
program, bit 5 for erase) will be set in the Status Register to indicate the operation
failed.
When WP# is at logic high, the boot block is unlocked and can be
programmed or erased.
NOTE: This feature is overridden and the boot block unlocked when RP# is at
VHH. See Section 3.4 for details on write protection.
BYTE# ENABLE: Not available on 28F004B. Controls whether the device
operates in the byte-wide mode (x8) or the word-wide mode (x16). BYTE# pin
must be controlled at CMOS levels to meet the CMOS current specification in the
standby mode.
When BYTE# is at logic low, the byte-wide mode is enabled, where data is
read and programmed on DQ0–DQ7 and DQ15/A–1 becomes the lowest order
address that decodes between the upper and lower byte. DQ8–DQ14 are tri-stated
during the byte-wide mode.
When BYTE# is at logic high, the word-wide mode is enabled, where data is
read and programmed on DQ0–DQ15.
DEVICE POWER SUPPLY: 5.0V ± 10%, 3.3 ± 0.3V, 2.7V–3.6V (BE/CE only)
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block, a voltage either of 5V ± 10% or 12V ± 5% must
be applied to this pin. When VPP < VPPLK all blocks are locked and protected
against Program and Erase commands.
GROUND: For all internal circuitry.
NO CONNECT: Pin may be driven or left floating.
12 PRELIMINARY

12 Page





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