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PA28F016SC-95 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer PA28F016SC-95
Beschreibung BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4/ 8/ AND 16 MBIT
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 42 Seiten
PA28F016SC-95 Datasheet, Funktion
E
PRELIMINARY
BYTE-WIDE
SmartVoltage FlashFile™ MEMORY FAMILY
4, 8, AND 16 MBIT
28F004SC, 28F008SC, 28F016SC
Includes Commercial and Extended Temperature Specifications
n SmartVoltage Technology
2.7 V (Read-Only), 3.3 V or 5 V VCC
and 3.3 V, 5 V, or 12 V VPP
n High-Performance
4, 8 Mbit 85 ns Read Access Time
16 Mbit 95 ns Read Access Time
n Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Block Write Lockout during Power
Transitions
n Enhanced Automated Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n Industry-Standard Packaging
40-Lead TSOP, 44-Lead PSOP
and 40 Bump µBGA* CSP
n High-Density 64-Kbyte Symmetrical
Erase Block Architecture
4 Mbit: Eight Blocks
8 Mbit: Sixteen Blocks
16 Mbit: Thirty-Two Blocks
n Extended Cycling Capability
100,000 Block Erase Cycles
n Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases ICC in Static Mode
n Automated Program and Block Erase
Command User Interface
Status Register
n SRAM-Compatible Write Interface
n ETOX™ V Nonvolatile Flash
Technology
Intel’s byte-wide SmartVoltage FlashFile™ memory family renders a variety of density offerings in the same
package. The 4-, 8-, and 16-Mbit byte-wide FlashFile memories provide high-density, low-cost, nonvolatile,
read/write storage solutions for a wide range of applications. Their symmetrically-blocked architecture, flexible
voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs,
and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage
applications. For secure code storage applications, such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the 4-, 8-, and 16-Mbit FlashFile memories offer three levels
of protection: absolute protection with VPP at GND, selective hardware block locking, or flexible software
block locking. These alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They come in
industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged
44-lead PSOP. Based on the 28F008SA architecture, the byte-wide SmartVoltage FlashFile memory family
enables quick and easy upgrades for designs that demand state-of-the-art technology.
December 1997
Order Number: 290600-003






PA28F016SC-95 Datasheet, Funktion
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
E
A block erase operation erases one of the device’s
64-Kbyte blocks typically within 1 second
(5 V VCC, 12 V VPP), independent of other blocks.
Each block can be independently erased 100,000
times (1.6 million block erases per device). A block
erase suspend operation allows system software to
suspend block erase to read data from or write data
to any other block.
Data is programmed in byte increments typically
within 6 µs (5 V VCC, 12 V VPP). A program
suspend operation permits system software to read
data or execute code from any other flash memory
array location.
To protect programmed data, each block can be
locked. This block locking mechanism uses a
combination of bits, block lock-bits and a master
lock-bit, to lock and unlock individual blocks. The
block lock-bits gate block erase and program
operations, while the master lock-bit gates block
lock-bit configuration operations. Lock-bit config-
uration operations (Set Block Lock-Bit, Set Master
Lock-Bit, and Clear Block Lock-Bits commands) set
and clear lock-bits.
The status register and RY/BY# output indicate
whether or not the device is busy executing or
ready for a new command. Polling the status
register, system software retrieves WSM feedback.
The RY/BY# output gives an additional indicator of
WSM activity by providing a hardware status signal.
Like the status register, RY/BY#-low indicates that
the WSM is performing a block erase, program, or
lock-bit configuration operation. RY/BY#-high
indicates that the WSM is ready for a new
command, block erase is suspended (and program
is inactive), program is suspended, or the device is
in deep power-down mode.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 1 mA at
5 V VCC.
When CE# and RP# pins are at VCC, the
component enters a CMOS standby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (tPHQV) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are
recognized.
1.3 Pinout and Pin Description
The family of devices is available in 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick) and
44-lead PSOP (Plastic Small Outline Package) and
40-bump µBGA* CSP (28F008SC and 28F016SC
only). Pinouts are shown in Figures 2, 3 and 4.
6 PRELIMINARY

6 Page









PA28F016SC-95 pdf, datenblatt
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
E
2.0 PRINCIPLES OF OPERATION
The byte-wide SmartVoltage FlashFile memories
include an on-chip WSM to manage block erase,
program, and lock-bit configuration functions. It
allows for: 100% TTL-level control inputs, fixed
power supplies during block erasure, program, and
lock-bit configuration, and minimal processor
overhead with RAM-like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the
device defaults to read array mode. Manipulation of
external memory control pins allow array read,
standby, and output disable operations.
Status register and identifier codes can be
accessed through the CUI independent of the VPP
voltage. High voltage on VPP enables successful
block erasure, program, and lock-bit configuration.
All functions associated with altering memory
contents—block erase, program, lock-bit
configuration, status, and identifier codes—are
accessed via the CUI and verified through the
status register.
Commands are written using standard micro-
processor write timings. The CUI contents serve as
input to the WSM that controls block erase,
program, and lock-bit configuration operations. The
internal algorithms are regulated by the WSM,
including pulse repetition, internal verification, and
margining of data. Addresses and data are
internally latched during write cycles. Writing the
appropriate command outputs array data, accesses
the identifier codes, or outputs status register data.
Interface software that initiates and polls progress
of block erase, program, and lock-bit configuration
can be stored in any block. This code is copied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system
software to suspend a block erase to read or write
data from any other block. Program suspend allows
system software to suspend a program to read data
from any other flash memory array location.
1FFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1A0000
19FFFF
190000
18FFFF
180000
17FFFF
170000
16FFFF
160000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
000000
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
16-Mbit
15
14
13
12
11
10
9
8-Mbit
8
7
6
5
4
4-Mbit
3
2
1
0
Figure 5. Memory Map
12 PRELIMINARY

12 Page





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