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P89LPC931FDH Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P89LPC931FDH
Beschreibung 8-bit microcontrollers with two-clock 80C51 core 4 kB/8 kB 3 V Flash with 256-byte data RAM
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
P89LPC931FDH Datasheet, Funktion
P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
4 kB/8 kB 3 V Flash with 256-byte data RAM
Rev. 04 — 06 January 2004
Product data
1. General description
The P89LPC930/931 is a single-chip microcontroller designed for applications
demanding high-integration, low cost solutions over a wide range of performance
requirements. The P89LPC930/931 is based on a high performance processor
architecture that executes instructions in two to four clocks, six times the rate of
standard 80C51 devices. Many system-level functions have been incorporated into
the P89LPC930/931 in order to reduce component count, board space, and system
cost.
2. Features
s A high performance 80C51 CPU provides instruction cycle times of 167-333 ns for
all instructions except multiply and divide when executing at 12 MHz. This is
6 times the performance of the standard 80C51 running at the same clock
frequency. A lower clock frequency for the same performance results in power
savings and reduced EMI.
s 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
s 4 kB/8 kB Flash code memory with 1 kB sectors, and 64-byte page size.
s Byte-erase allowing code memory to be used for data storage.
s Flash program operation completes in 2 ms.
s Flash erase operation completes in 2 ms.
s 256-byte RAM data memory.
s Two 16-bit counter/timers. Each timer may be configured to toggle a port output
upon timer overflow or to become a PWM output.
s Real-Time clock that can also be used as a system timer.
s Two analog comparators with selectable inputs and reference source.
s Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities.
s 400 kHz byte-wide I2C-bus communication port.
s SPI communication port.
s Eight keypad interrupt inputs, plus two additional external interrupt inputs.
s Four interrupt priority levels.
s Watchdog timer with separate on-chip oscillator, requiring no external
components. The Watchdog time-out time is selectable from 8 values.
s Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available.






P89LPC931FDH Datasheet, Funktion
Philips Semiconductors
P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
5.2 Pin description
Table 3: Pin description
Symbol
Pin
Type
P0.0 - P0.7
3, 26, 25, I/O
24, 23, 22,
20, 19
3 I/O
O
I
26 I/O
I
I
25 I/O
I
I
24 I/O
I
I
23 I/O
I
I
22 I/O
I
I
20 I/O
O
I
19 I/O
I/O
I
Description
Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset
Port 0 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 0 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
8.11.1 “Port configurations” and Table 7 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
P0.0 — Port 0 bit 0.
CMP2 — Comparator 2 output.
KBI0 — Keyboard input 0.
P0.1 — Port 0 bit 1.
CIN2B — Comparator 2 positive input B.
KBI1 — Keyboard input 1.
P0.2 — Port 0 bit 2.
CIN2A — Comparator 2 positive input A.
KBI2 — Keyboard input 2.
P0.3 — Port 0 bit 3.
CIN1B — Comparator 1 positive input B.
KBI3 — Keyboard input 3.
P0.4 — Port 0 bit 4.
CIN1A — Comparator 1 positive input A.
KBI4 — Keyboard input 4.
P0.5 — Port 0 bit 5.
CMPREF — Comparator reference (negative) input.
KBI5 — Keyboard input 5.
P0.6 — Port 0 bit 6.
CMP1 — Comparator 1 output.
KBI6 — Keyboard input 6.
P0.7 — Port 0 bit 7.
T1 — Timer/counter 1 external count input or overflow output.
KBI7 — Keyboard input 7.
9397 750 12284
Product data
Rev. 04 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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Table 4: Special function registers
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
addr. MSB
LSB
Reset value
Hex Binary
Bit address E7 E6 E5 E4 E3 E2 E1 E0
ACC*
Accumulator
E0H
00 00000000
AUXR1
B*
BRGR0[2]
BRGR1[2]
BRGCON
CMP1
CMP2
DIVM
DPTR
DPH
DPL
FMADRH
FMADRL
FMCON
FMDATA
I2ADR
I2CON*
I2DAT
Auxiliary function register
A2H CLKLP
Bit address F7
B register
F0H
Baud rate generator rate
LOW
BEH
Baud rate generator rate
HIGH
BFH
Baud rate generator control BDH
-
Comparator 1 control register ACH
-
Comparator 2 control register ADH
-
CPU clock divide-by-M
control
95H
Data pointer (2 bytes)
Data pointer HIGH
83H
Data pointer LOW
82H
Program Flash address HIGH E7H
-
Program Flash address LOW E6H
Program Flash Control
(Read)
E4H BUSY
Program Flash Control
(Write)
FMCMD.
7
Program Flash data
E5H
I2C slave address register
DBH I2ADR.6
Bit address DF
I2C control register
D8H
-
I2C data register
DAH
EBRR
F6
-
-
-
-
-
FMCMD.
6
I2ADR.5
DE
I2EN
ENT1
F5
-
CE1
CE2
-
-
FMCMD.
5
I2ADR.4
DD
STA
ENT0
F4
-
CP1
CP2
-
-
FMCMD.
4
I2ADR.3
DC
STO
SRST
F3
-
CN1
CN2
-
HVA
FMCMD.
3
I2ADR.2
DB
SI
0
F2
-
OE1
OE2
-
HVE
FMCMD.
2
I2ADR.1
DA
AA
-
F1
SBRGS
CO1
CO2
SV
FMCMD.
1
I2ADR.0
D9
-
DPS
F0
00[1]
00
00
00
BRGEN 00[6]
CMF1 00[1]
CMF2 00[1]
00
00
00
00
00
OI 70
FMCMD.
0
00
GC 00
D8
CRSEL 00
000000x0
00000000
00000000
00000000
xxxxxx00
xx000000
xx000000
00000000
00000000
00000000
00000000
00000000
01110000
00000000
00000000
x00000x0

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