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P89C739 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P89C739
Beschreibung 8-bit Flash microcontrollers
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 64 Seiten
P89C739 Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
P89C738; P89C739
8-bit Flash microcontrollers
Product specification
Supersedes data of 1997 Dec 15
File under Integrated Circuits, IC20
1998 Apr 07






P89C739 Datasheet, Funktion
Philips Semiconductors
8-bit Flash microcontrollers
6 PINNING INFORMATION
6.1 Pin configuration
Product specification
P89C738; P89C739
handbook, full pagewidth
P1.5 7
P1.6 8
P1.7 9
RST 10
P3.0/RXD/data 11
n.c. 12
P3.1/TXD/clock 13
P3.2/INT0 14
P3.3/INT1 15
P3.4/T0 16
P3.5/T1 17
P89C738ABA
39 P0.4/AD4
38 P0.5/AD5
37 P0.6/AD6
36 P0.7/AD7
35 EA/VPP
34 n.c.
33 ALE/WE
32 PSEN
31 P2.7/A15
30 P2.6/A14
29 P2.5/A13
MGK185
Fig.3 Pin configuration for PLCC44 package; for more information on the version see Chapter 3.
1998 Apr 07
6

6 Page









P89C739 pdf, datenblatt
SYMBOL
P2.0/A8 to
P2.2/A10
P2.3/A11 to
P2.4/A12
P2.5/A13 to
P2.7/A15
PSEN
ALE/WE(2)
EA/VPP
P0.7/AD7 to
P0.4/AD4
P0.3/AD3 to
P0.2/AD2
P0.1/AD1 to
P0.0/AD0
VDD
PLCC68 QFP64
54 to 56 44 to 46
PIN(1)
PLCC44 QFP44
38 to 34 24 to 31
58 to 59 48 to 49
61, 64
and 65
67
51, 54
and 55
56
23 to 25
26 32
68 57 27 33
2 59 29 35
3, 5, 6
and 9
11 to 12
60, 61, 62 30 to 33
and 1
3 to 4
22 to 21
36 to 43
14 to 15 6 to 7
20 to 19
DIP40
21 to 28
29
30
31
32 to 39
DESCRIPTION
Port 2: P2.0 to P2.7; 8-bit quasi-bidirectional I/O Port with internal
pull-ups. Port 2 can sink/source one TTL (= 4 LSTTL) input. It can
drive CMOS inputs without external pull-ups.
Port 2 alternative functions are: A8 to A15; during access to
external memories (RAM/ROM) that use 16-bit addresses (MOVX
@DPTR) Port 2 emits the high-order address byte (A8 to A15).
Program Store Enable output: read strobe to the external program
memory via Port 0 and Port 2. It is activated twice each machine
cycle during fetches from external program memory.
When executing out of external program memory two activations of
PSEN are skipped during each access to external data memory.
PSEN is not activated (remains HIGH) during no fetches from
external program memory. PSEN can sink/source 8 LSTTL inputs. It
can drive CMOS inputs without external pull-ups.
Address Latch Enable output: latches the lower byte of the
address during access to external memory in normal operation. It is
activated every six oscillator periods except during an external data
memory access. ALE can sink/source 8 LSTTL inputs. It can drive
CMOS inputs without an external pull-up.
WE: Write Enable.
External Access input: when during reset, EA is held at a TTL
HIGH level, the CPU executes from the internal program ROM.
When EA is held at a TTL LOW level during reset, the CPU executes
out of external program memory via Port 0 and Port 2. EA is not
allowed to float. EA is latched during reset and don’t care after reset.
VPP: programming supply voltage.
Port 0: P0.7 to P0.0; 8-bit open-drain bidirectional I/O port. It is also
the multiplexed low-order address and data bus during accesses to
external memory: AD0 to AD7. During these accesses internal
pull-ups are activated. Port 0 can sink/source 8 LSTTL inputs.
17 9
18 44 40 Power supply (+5 V) pin for normal operation, Idle mode and
Power-down mode.

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