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P87C754EBDDB Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P87C754EBDDB
Beschreibung 80C51 8-bit microcontroller family 4K/256 OTP/ROM/ DAC/ comparator/ UART/ reference
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 26 Seiten
P87C754EBDDB Datasheet, Funktion
INTEGRATED CIRCUITS
83C754/87C754
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
Preliminary specification
Supersedes data of 1997 Dec 03
IC20 Data Handbook
1998 Apr 23
Philips
Semiconductors






P87C754EBDDB Datasheet, Funktion
Philips Semiconductors
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
Preliminary specification
83C754/87C754
Serial Port Control Register
The serial port control and status register is the Special Function
Register SCON, shown in Figure 1. This register contains not only
the mode selection bits, but also the 9th data bit for transmit and
receive (TB8 and RB8), and the serial port interrupt bits (TI and RI).
Baud Rates
The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator
Frequency / 12. The baud rate in Mode 2 depends on the value of
bit SMOD in Special function Register PCON. If SMOD = 0 (which is
the value on reset), the baud rate is 1/64 the oscillator frequency.
If SMOD = 1, the baud rate is 1/32 the oscillator frequency.
Mode
2
Baud
Rate
+
2SMOD
64
(Oscillator Frequency)
In the 8XC754, the baud rates in Modes 1 and 3 are determined by
the Timer 1 overflow rate.
Using Timer 1 to Generate Baud Rates
When Timer 1 is used as the baud rate generator, the baud rates in
Modes 1 and 3 are determined by the Timer 1 overflow rate and the
value of SMOD as follows:
Mode
1,
3
Baud
Rate
+
2SMOD
32
(Timer 1 Overflow Rate)
The Timer 1 interrupt should be disabled in this application. The
Timer itself can be configured for either “timer” or “counter”
operation, and in any of its 3 running modes. In the most typical
applications, it is configured for “timer” operation, in the auto-reload
mode (high nibble of TMOD = 0010B). In that case the baud rate is
given by the formula:
Mode
1,
3
Baud
Rate
+
2SMOD
32
Oscillator Frequency
12 [256 * (TH1)]
One can achieve very low baud rates with Timer 1 by leaving the
Timer 1 interrupt enabled, and configuring the Timer to run as a
16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1
interrupt to do a 16-bit software reload. Figure 2 lists various
commonly used baud rates and how they can be obtained from
Timer 1.
SM2
REN
TB8
RB8
TI
RI
MSB
LSB
SM0 SM1 SM2 REN TB8 RB8 TI RI
Where SM0, SM1 specify the serial port mode, as follows:
SM0
0
0
1
1
SM1
0
1
0
1
Mode
0
1
2
3
Description
shift register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
fOSC/ 12
variable
fOSC/64 or fOSC/32
variable
Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then Rl will not be
activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI will not be activated if a valid stop bit was not
received. In Mode 0, SM2 should be 0.
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is the stop bit that was received. In Mode 0,
RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other
modes, in any serial transmission. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other
modes, in any serial reception (except see SM2). Must be cleared by software.
SU00120
Figure 1.
Baud Rate
fOSC
SMOD
C/T
Mode 0 Max: 1.67MHz
Mode 2 Max: 625k
Mode 1, 3 Max: 104.2k
19.2k
9.6k
4.8k
2.4k
1.2k
137.5
110
110
20MHz
20MHz
20MHz
11.059MHz
11.059MHz
11.059MHz
11.059MHz
11.059MHz
11.986MHz
6MHz
12MHz
XX
1X
10
10
00
00
00
00
00
00
00
Figure 2. Timer 1 Generated Commonly Used Baud Rates
Timer 1
Mode
Reload Value
XX
XX
2 FFH
2 FDH
2 FDH
2 FAH
2 F4H
2 E8H
2 1DH
2 72H
1 FEEBH
1998 Apr 23
6

6 Page









P87C754EBDDB pdf, datenblatt
Philips Semiconductors
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
Preliminary specification
83C754/87C754
CMOD Address = OD9H
Reset Value = 00XX X000B
Bit Addressable
CIDL WDTE
CPS1 CPS0
ECF
Bit: 7 6 5 4 3 2 1 0
Symbol Function
CIDL
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
WDTE
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module. WDTE = 1 enables it.
– Not implemented, reserved for future use.*
CPS1
PCA Count Pulse Select bit 1.
CPS0
PCA Count Pulse Select bit 0.
CPS1 CPS0 Selected PCA Input**
00
01
10
0 Internal clock, fOSC ÷ 12
1 Internal clock, fOSC ÷ 4
2 Timer 0 overflow
11
3 External clock at ECI/P3.1 pin (max. rate = fOSC ÷ 8)
ECF
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
** fOSC = oscillator frequency
SU00675A
Figure 8. CMOD: PCA Counter Mode Register
CCON Address = OD8H
Reset Value = 00X0 0000B
Symbol
CF
CR
CCF
Bit Addressable
CF CR –– CCF –– –– –– ––
Bit: 7 6 5 4 3 2 1 0
Function
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
Not implemented, reserved for future use*.
PCA Module interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU00676A
Figure 9. CCON: PCA Counter Control Register
1998 Apr 23
12

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