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P83CE560 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P83CE560
Beschreibung 8-bit microcontroller
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
P83CE560 Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
P8xCE560
8-bit microcontroller
Product specification
File under Integrated Circuits, IC20
1997 Aug 01






P83CE560 Datasheet, Funktion
Philips Semiconductors
8-bit microcontroller
5 FUNCTIONAL DIAGRAM
Product specification
P8xCE560
handbook, full pagewidth
XTAL1
XTAL2
EA/VPP (1)
PSEN
ALE/PROG (1)
PWM0
PWM1
SCL
SDA
ADEXS
alternative function
Vref(p)(A)
Vref(n)(A)
STADC
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
PORT 5
0
1
2
3
4
5
6
7
CMSR0
CMSR1
CMSR2
CMSR3
CMSR4
CMSR5
CMT0
CMT1
PORT 4
0
1
2
3
4
5
6
7
RSTIN
RSTOUT
EW
P8xCE560
MBH075
SELXTAL1
XTAL4
XTAL3
0
1
2
3
4 PORT 0
5
6
7
0
1
2
3
4 PORT 1
5
6
7
0
1
2
3 PORT 2
4
5
6
7
0
1
2
3
4 PORT 3
5
6
7
VSSA
VDDA
VSS
VDD
(2)
alternative function
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
LOW ORDER
ADDRESS
AND
DATA BUS
CT0I/INT2
CT1I/INT3
CT2I/INT4
CT3I/INT5
T2
RT2
A8
A9
A10
A11
HIGH ORDER
ADDRESS
A12 BUS
A13
A14
A15
RXD/DATA
TXD/CLOCK
INT0
INT1
T0
T1
WR
RD
(1) Only the P87CE560 with an alternative function.
(2) VDDA/VSSA - 2 analog supply pairs;
VDD/VSS - 4 digital supply pairs.
Fig.2 Functional diagram.
1997 Aug 01
6

6 Page









P83CE560 pdf, datenblatt
Philips Semiconductors
8-bit microcontroller
Product specification
P8xCE560
An access to external Data Memory locations higher than
1791 will be performed with the MOVX @DPTR
instructions in the same way as in the 80C51 structure, so
with P0 and P2 as data/address bus and P3.6 and P3.7 as
write and read timing signals.
Note that the external Data Memory cannot be accessed
with R0 and R1 as address pointer if the AUX-RAM is
enabled (ARD = 0, default).
8.2.4 AUX-RAM PAGE REGISTER (XRAMP)
The AUX-RAM Page Register is used to select one of
seven 256-bytes pages of the internal 1792 bytes
AUX-RAM for MOVX-accesses via R0 or R1. Its reset
value is ‘XXXX X000B’.
Table 4 AUX-RAM Page Register (address FAH)
7
XRAMPx
6
XRAMPx
5
XRAMPx
4
XRAMPx
3
XRAMPx
2
XRAMP2
1
XRAMP1
0
XRAMP0
Table 5 Description of XRAMP bits
BIT
7 to 3
SYMBOL
XRAMPx
2 to 0
XRAMP2 to XRAMP0
FUNCTION
Reserved for future use. During read XRAMPx = undefined; a write
operation must write logic 0s to these locations.
AUX-RAM page select bits 2 to 0; see Table 6.
Table 6 Memory locations for all possible MOVX-accesses
X = don’t care.
ARD(1) XRAMP2 XRAMP1 XRAMP0
MEMORY LOCATIONS
MOVX @Ri,A and MOVX A,@Ri instructions access
0 0 0 0 AUX-RAM locations 0 to 255 (reset condition)
0 0 0 1 AUX-RAM locations 256 to 511
0 0 1 0 AUX-RAM locations 512 to 767
0 0 1 1 AUX-RAM locations 768 to 1023
0 1 0 0 AUX-RAM locations 1024 to 1279
0 1 0 1 AUX-RAM locations 1280 to 1535
0 1 1 0 AUX-RAM locations 1536 to 1791
0 1 1 1 No valid memory access; reserved for future use
1 X X X External RAM locations 0 to 255
MOVX @DPTR,A and MOVX A,@DPTR instructions access
0 X X X AUX-RAM locations 0 to 1791 (reset condition);
External RAM locations 1792 to 65535
1 X X X External RAM locations 0 to 65535
Note
1. ARD: AUX-RAM disable, is a bit in SFR PCON (bit PCON.6); see Section 15.5.
1997 Aug 01
12

12 Page





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