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P83C851IBB Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P83C851IBB
Beschreibung CMOS single-chip 8-bit microcontroller with on-chip EEPROM
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 22 Seiten
P83C851IBB Datasheet, Funktion
INTEGRATED CIRCUITS
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
Product specification
Supersedes data of 1992 Nov 25
IC20 Data Handbook
1998 Jul 03
Philips
Semiconductors






P83C851IBB Datasheet, Funktion
Philips Semiconductors
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
Product specification
80C851/83C851
Table 1. 8XC851 Special Function Registers
SYMBOL DESCRIPTION
ACC*
Accumulator
DIRECT
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
RESET
ADDRESS MSB
LSB VALUE
E0H
E7 E6
E5
E4
E3
E2
E1
E0 00H
B* B register
F0H
F7 F6
F5
F4
F3
F2
F1
F0 00H
EF EE
ED
EC
EB
EA
E9
E8
DPTR:
DPH
DPL
Data pointer
(2 bytes):
High byte
Low byte
83H
82H
00H
00H
EADRH#
EADRL#
EEPROM addr
reg-high
EEPROM addr
reg-low
F3H
F2H
80H
00H
ECNTRL# EEPROM control reg
EDAT#
EEPROM data
register
F6H
F4H
IFE EEINT EWP
– ECNTR ECNTR ECNTR ECNTR 00H
L3 L2 L1 L0
xxH
ETIM#
EEPROM timer
register
F5H
08H
BF BE
BD
BC
BB
BA
B9
B8
IP* Interrupt priority
B8H – – – PS PT1 PX1 PT0 PX0 xxx00000B
IE*
P0*
P1*
P2*
P3*
PCON
Interrupt enable
Port 0
Port 1
Port 2
Port 3
Power control
AF AE
A8H EA –
80H 87 86
90H 97 96
A0H A7 A6
B0H B7 B6
87H SMOD –
AD
85
95
A5
B5
AC AB AA A9 A8
ES ET1 EX1 ET0 EX0 0xx00000B
84 83 82 81 80 FFH
94 93 92 91 90 FFH
A4 A3 A2 A1 A0 FFH
B4 B3 B2 B1 B0 FFH
– GF1 GF0 PD IDL 0xxx0000B
PSW*
SBUF
Program status word
Serial data buffer
D0H
99H
SCON*
SP
Serial port control
Stack pointer
98H
81H
TCON*
Timer/counter con-
trol
88H
D7 D6
CY AC
D5 D4 D3 D2
F0 RS1 RS0 OV
D1
9F 9E
9D
9C
9B
9A
SM0 SM1 SM2 REN TB8 RB8
99
TI
8F 8E
8D
8C
8B
8A
89
TF1 TR1 TF0 TR0 IE1 IT1 IE0
D0
P 00H
xxxxxxxxB
98
RI 00H
07H
88 00H
IT0 00H
TMOD
Timer/counter mode
89H GATE C/T M1
M0 GATE C/T
M1
M0 00H
TH0 Timer 0 high byte
8CH
00H
TH1 Timer 1 high byte
8DH
00H
TL0 Timer 0 low byte
8AH
00H
TL1 Timer 1 low byte
8BH
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
00H
1998 Jul 03
6

6 Page









P83C851IBB pdf, datenblatt
Philips Semiconductors
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
Product specification
80C851/83C851
AC ELECTRICAL CHARACTERISTICS1, 2
16 MHz Version
SYMBOL FIGURE
PARAMETER
1/tCLCL
tLHLL
tAVLL
tLLAX
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
Data Memory
4
4
4
4
4
4
4
4
4
4
4
4
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
tRLRH
5
tWLWH
5
tRLDV
5
tRHDX
5
tRHDZ
5
tLLDV
5
tAVDV
5
tLLWL
5, 6
tAVWL
5, 6
tQVWH
6
tQVWX
6
tWHQX
6
tRLAZ
5
tWHLH
5, 6
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to RD or WR low
Data setup time before WR
Data valid to WR transition
Data hold after WR
RD low to address float
RD or WR high to ALE high
tCHCX
8 High time
tCLCX
8 Low time
tCLCH
8 Rise time
tCHCL
8 Fall time
Erase/write timer constant3
tE/W
tE
tW
tS
NE/W
Erase/write cycle time
Erase time
Write time
Data retention time4
Erase/write cycles5
16MHz CLOCK
MIN MAX
85
8
28
150
23
143
83
0
38
208
10
275
275
148
0
55
350
398
138 238
120
288
3
13
0
23 103
20
20
20
20
4
2
2
10
10,000
20
10
10
VARIABLE CLOCK
MIN MAX
1.2 16
2tCLCL–40
tCLCL–55
tCLCL–35
tCLCL–40
3tCLCL–45
0
4tCLCL–100
3tCLCL–105
tCLCL–25
5tCLCL–105
10
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6tCLCL–100
6tCLCL–100
0
3tCLCL–50
4tCLCL–130
7tCLCL–150
tCLCL–60
tCLCL–50
tCLCL–40
20
20
5tCLCL–165
2tCLCL–70
8tCLCL–150
9tCLCL–165
3tCLCL+50
0
tCLCL+40
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
2
2
10
10,000
20 ms
10 ms
10 ms
years
cycles
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. The power-off fall-time of VDD must be less than 1ms to prevent an overwrite pulse from being generated in the EEPROM which can cause
spurious parasitic writing to EEPROM cells. If the VDD power-off full-time is greater than 1ms, a power-off reset signal should be generated
to prevent this condition from occurring.
4. Test condition: Tamb = +55°C.
5. Number of erase/write cycles for each EEPROM byte.
1998 Jul 03
12

12 Page





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