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P83C654IBBB Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P83C654IBBB
Beschreibung CMOS single-chip 8-bit microcontroller
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 24 Seiten
P83C654IBBB Datasheet, Funktion
INTEGRATED CIRCUITS
83C654
CMOS single-chip 8-bit microcontroller
Product specification
Supersedes data of 1996 Aug 15
IC20 Data Handbook
1998 Jan 06
Philips
Semiconductors






P83C654IBBB Datasheet, Funktion
Philips Semiconductors
CMOS single-chip 8-bit microcontroller
Product specification
83C654
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP PLCC QFP TYPE NAME AND FUNCTION
VSS 20 22 6, 16, I Ground: 0V reference. With the QFP package all VSS pins (VSS1 to VSS4) must be
28, 39
connected.
VDD
40 44 38
I Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
P0.0–0.7
39–32 43–36 37–30
I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and data memory. In this
application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7
P1.6
P1.7
1–8 2–9 40–44, I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7
1–3 which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL).
Alternate functions include:
78
2 I/O
SCL: I2C-bus serial port clock line.
89
3 I/O
SDA: I2C-bus serial port data line.
P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte
during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit
addresses (MOV @Ri), port 2 emits the contents of the P2 special function register.
P3.0–P3.7 10–17 11,
5,
13–19 7–13
10 11
5
11 13
7
12 14
8
13 15
9
14 16 10
15 17
11
16 18 12
17 19 13
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
(See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51
family, as listed below:
I RxD (P3.0): Serial input port
O TxD (P3.1): Serial output port
I INT0 (P3.2): External interrupt
I INT1 (P3.3): External interrupt
I T0 (P3.4): Timer 0 external input
I T1 (P3.5): Timer 1 external input
O WR (P3.6): External data memory write strobe
O RD (P3.7): External data memory read strobe
RST
ALE
9 10
4
I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to VSS permits a power-on reset using only an external
capacitor to VDD.
30 33 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency. Note that one ALE pulse is skipped during each access to external data
memory.
PSEN
29 32 26
O Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It is
activated twice each machine cycle during fetches from the external program memory. When
executing out of external program memory two activations of PSEN are skipped during each
access to external data memory. PSEN is not activated (remains HIGH) during no fetches
from external program memory. PSEN can sink/source 8 LSTTL inputs and can drive CMOS
inputs without external pull–ups.
EA
31 35 29
I External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out
of the internal program memory ROM provided the Program Counter is less than 16384. If
during a RESET, EA is held a TTL LOW level, the CPU executes out of external program
memory. EA is not allowed to float.
XTAL1
19 21 15
I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2
18 20 14
O Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VDD + 0.5V or VSS – 0.5V, respectively.
1998 Jan 06
6

6 Page









P83C654IBBB pdf, datenblatt
Philips Semiconductors
CMOS single-chip 8-bit microcontroller
Product specification
83C654
AC ELECTRICAL CHARACTERISTICS1, 2 (16 MHz type)
16MHz CLOCK
VARIABLE CLOCK
SYMBOL FIGURE
PARAMETER
MIN MAX
MIN
MAX
1/tCLCL
tLHLL
tAVLL
tLLAX
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
Data Memory
2
2
2
2
2
2
2
2
2
2
2
2
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
3.5 16
85 2tCLCL–40
8 tCLCL–55
28 tCLCL–35
150 4tCLCL–100
23 tCLCL–40
143 3tCLCL–45
83 3tCLCL–105
00
38 tCLCL–25
208 5tCLCL–105
10 10
tRLRH
3, 4 RD pulse width
275 6tCLCL–100
tWLWH
3, 4 WR pulse width
275 6tCLCL–100
tRLDV
3, 4 RD low to valid data in
148
tRHDX
3, 4 Data hold after RD
00
tRHDZ
3, 4 Data float after RD
55
tLLDV
3, 4 ALE low to valid data in
350
tAVDV
3, 4 Address to valid data in
398
tLLWL
3, 4 ALE low to RD or WR low
138 238 3tCLCL–50
tAVWL
3, 4 Address valid to WR low or RD low
120 4tCLCL–130
tQVWX
3, 4 Data valid to WR transition
3 tCLCL–60
tDW 3, 4 Data setup time before WR
288 7tCLCL–150
tWHQX
3, 4 Data hold after WR
13 tCLCL–50
tRLAZ
3, 4 RD low to address float
0
tWHLH
3, 4 RD or WR high to ALE high
23 103 tCLCL–40
Shift Register
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
5 Serial port clock cycle time3
5 Output data setup to clock rising edge3
5 Output data hold after clock rising edge3
5 Input data hold after clock rising edge3
5 Clock rising edge to input data valid3
0.75
492
80
0
12tCLCL
10tCLCL–133
2tCLCL–117
0
492
External Clock
tCHCX
tCLCX
tCLCH
tCHCL
6 High time3
6 Low time3
6 Rise time3
6 Fall time3
20
20
20
20
20
20
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.
5tCLCL–165
2tCLCL–70
8tCLCL–150
9tCLCL–165
3tCLCL+50
0
tCLCL+40
10tCLCL–133
tCLCL – tCLCX
tCLCL – tCHCX
20
20
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
1998 Jan 06
12

12 Page





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