P83C576EHBB Datasheet PDF - NXP Semiconductors
| Part Number | P83C576EHBB | |
| Description | 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ 6 channel 10-bit A/D/ 4 comparators/ failure detect circuitry/ watchdog timer | |
| Manufacturers | NXP Semiconductors | |
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INTEGRATED CIRCUITS
83C576/87C576
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D,
4 comparators, failure detect circuitry, watchdog timer
Product specification
Supersedes data of 1998 Jan 06
IC20 Data Handbook
1998 Jun 04
Philips
Semiconductors
|
| |
 
Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
Product specification
83C576/87C576
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP LCC QFP
VSS
VCC
P0.0-0.7
20
40
39-32
22
44
43-36
16
38
37-30
P1.0-P1.5
3-8 5-9 42-44
1-3
P2.0-P2.7
3
4
5
6
7
8
21-28
4
5
6
7
8
9
24-31
42
43
44
1
2
3
18-25
21 24 18
22 25 19
23 26 20
24 27 21
25 28 22
26 29 23
27 30 24
28 31 25
TYPE
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NAME AND FUNCTION
Ground: 0V reference.
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
Port 0: Port 0 is a bidirectional I/O port. Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and data memory (see Note 5). In this
application, it uses strong internal pull-ups when emitting 1s. Port 0 also receives code bytes
during parallel EPROM programming and outputs code bytes during verification. External
pull-ups are required during program verification. During reset, the port register is loaded
with 1’s. Port 0 has 4 output modes selected on a per bit basis by writing to the P0M1 and
P0M2 Special Function Registers as follows:
P0M1.x
P0M2.x
Mode Description
0 0 Open drain (default). See Note 1.
0 1 Weak pullup. See Note 2.
1 0 High impedance. See Note 3.
1 1 Push-pull. See Note 4.
Port 0 is also the data I/O port for the Universal Peripheral Interface (UPI). When the UPI is
enabled, port 0 must be configured as High-Z by the user. Input/Output through P0 is
controlled by pin CS, WR, RD, and A0. Output is push-pull when enabled.
Port 1: Port 1 is a 6-bit bidirectional I/O port with Schmitt trigger inputs. Port 1 receives the control
signals during program memory verification and parallel EPROM programming. During reset, port
1 is configured as a high impedance analog input port. Digital push-pull outputs are enabled by
writing 1’s to the P1M1 register. The programmer must take care to prevent digital outputs from
switching while an A/D conversion is in progress. Port 1 has 3 output modes selected on a per bit
basis by writing to the P1M1 and P1M2 special function registers as follows:
P1M1.X
P1M2.X Mode Description
0 0 A/D only. (High impedance)
0 1 Digital input only. High impedance (default).
1 X Push-pull.
Port 1 pins also serve alternate functions as follows:
P1.0/ADIN0
P1.1/ADIN1
P1.2/ADIN2
P1.3/ADIN3
P1.4/ADIN4
P1.5/ADIN5
Port 2: Port 2 is an 8-bit bidirectional I/O port. Port 2 emits the high-order address byte
during accesses to external program and data memory that use 16-bit addresses (MOVX
@DPTR) (see Note 5). In this application, it uses strong internal pull-ups when emitting 1s.
Port 2 receives the high-order address byte during program verification and parallel EPROM
programming. During reset, the port 2 pullups are turned on synchronously, and the port
register is loaded with 1’s. Port 2 has the following output modes which can be selected on a
per bit basis by writing to P2M1 and P2M0:
P2M1.X
0
0
1
1
P2M2.X
0
1
0
1
Mode Description
Open drain. See Note 1.
Weak pullup (default). See Note 2.
High impedance. See Note 3.
Push-pull. See Note 4.
Port 2 pins serve alternate functions as follows:
P2.0 CEX0 PCA module 0 external I/O
CMP0 comparator 0 output
P2.1
CEX1 PCA module 1 external I/O
CMP1 comparator 1 output
P2.2
CEX2 PCA module 2 external I/O
CMP2 comparator 2 output
P2.3
CEX3 PCA module 3 external I/O
CMP3 comparator 3 output
P2.4
T2EX timer 2 capture input
A0 UPI address input
P2.5
T2
CS
timer 2 external I/O — clock-out (programmable)
UPI chip select input
P2.6
CEX4 PCA module 4 external I/O
PWM0 Pulse width modulator 0 output
P2.7
ECI PCA count input
PWM1 Pulse width modulator 1 output
1998 Jun 04
5
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| Information | Total 30 Pages | |
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