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P83C566 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P83C566
Beschreibung Microcontrollers for PAL/SECAM TV with OSD and VST
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
P83C566 Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
P8xCx66 family
Microcontrollers for PAL/SECAM
TV with OSD and VST
Product specification
File under Integrated Circuits, IC20
1999 Mar 10






P83C566 Datasheet, Funktion
Philips Semiconductors
Microcontrollers for PAL/SECAM TV
with OSD and VST
5 PINNING INFORMATION
5.1 Pinning
Product specification
P8xCx66 family
handbook, halfpage
P5.0/TPWM 1
42 VDDD
P5.1/PWM0 2
41 P1.7
P5.2/PWM1 3
40 P1.6/SDA
P5.3/PWM2 4
39 P1.5/SCL
P5.4/PWM3 5
38 P1.4/T1
P5.5/PWM4 6
37 P1.3/INT0
P5.6/PWM5 7
36 P1.2/T0
P5.7/PWM6 8
35 P1.1/INT1
P3.0/ADC0 9
34 P1.0
P3.1/ADC1 10
33 RESET
P3.2/ADC2 11 P8xCx66 32 XTALOUT
P3.3/PWM7 12
31 XTALIN
P0.0 13
P0.1 14
P0.2 15
30 VPP
29 VSSA
28 VDDA
P0.3 16
27 VSYNC
P0.4 17
26 HSYNC
P0.5 18
25 FB
P0.6 19
24 R
P0.7 20
23 G
VSSD 21
22 B
MGL301
1999 Mar 10
Fig.2 Pin configuration (SDIP42).
6

6 Page









P83C566 pdf, datenblatt
Philips Semiconductors
Microcontrollers for PAL/SECAM TV
with OSD and VST
Product specification
P8xCx66 family
7 I/O FACILITY
7.1 I/O ports
The SDIP42 package has 28 I/O lines treated as
28 individual addressable bits or as 3 parallel 8-bit
addressable ports (Ports 0, 1 and 5) and one 4-bit port
(Port 3).
When these 28 I/O lines are used as input ports, the
corresponding bits in SFRs P0, P1, P3 and P5 should be
set to a logic 1 to facilitate the external input signal.
Ports 1, 3 and 5 also perform the following alternative
functions.
Port 1. Used for a number of special functions:
Provides the external interrupt inputs (INT0 and INT1)
Provides the 16-bit timer/counter inputs (T0 and T1)
Provides the I2C-bus data and clock signals (SDA and
SCL)
P1.0 and P1.7 can be used as external interrupt inputs.
Port 3. Only 4 lines available for alternative functions:
7-bit PWM output (PWM7)
ADC inputs ADC0 to ADC2.
Port 5.
Provides the 14-bit PWM output (TPWM)
7-bit PWMs outputs (PWM0 to PWM6).
To enable the alternative functions of Ports 1, 3 and 5, the
port bit latch of its associated SFR must contain a logic 1.
Each port consists of a latch (SFRs P0, P1, P3 and P5), an
output driver and an input buffer.
7.2 Port configurations
1. Open-drain quasi-bidirectional I/O with n-channel
pull-down (see Fig.6). Use as an output requires the
connection of an external pull-up resistor. Use as an
input requires to write a logic 1 to the port latch before
reading the port line.
2. Push-pull; gives drive capability of the output in both
polarities, see Fig.7.
handbook, halfpage
Q
from port latch
input data
read port pin
n
INPUT
BUFFER
I/O pin
MGK547
handbook, halfpage
Q
from port latch
strong pull-up
+5 V
p1
n
output pin
MGM679
Fig.6 Open-drain port.
Fig.7 Push-pull port.
1999 Mar 10
12

12 Page





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