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P83C280 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P83C280
Beschreibung Microcontrollers for monitors with DDC interface/ auto-sync detection and sync proc.
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
P83C280 Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
P83Cx80; P87C380
Microcontrollers for monitors
with DDC interface, auto-sync
detection and sync proc.
Product specification
File under Integrated Circuits, IC20
1997 Dec 12






P83C280 Datasheet, Funktion
Philips Semiconductors
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
5 PINNING INFORMATION
5.1 Pinning
Product specification
P83Cx80; P87C380
handbook, halfpage
PWM7/P2.7 1
42 PWM8/CLAMP/P3.0
PWM6/P2.6 2
41 PWM9/PATOUT/P3.1
PWM5/P2.5 3
40 PWM10/P1.7
PWM4/P2.4 4
39 SCL/P1.0
PWM3/P2.3 5
38 SDA/P1.1
PWM2/P2.2 6
37 SCL1/P1.2
PWM1/P2.1 7
36 SDA1/P1.3
PWM0/P2.0 8
35 INT1/VPP
XTAL1 9
XTAL2 10
VDD 11
VSS 12
P83C880
P83C180
P83C280
P83C380
P87C380
34 ADC1/P3.3
33 ADC0/P3.2
32 VDDA
31 VSSA
HSYNCin/PROG 13
30 DAC3
HSYNCout/P1.5 14
29 DAC2
CSYNCin/P1.6 15
28 DAC1
VSYNCin/OE 16
27 DAC0
VSYNCout/P1.4 17
26 RESET
P0.7 18
25 P0.0
P0.6 19
24 P0.1
P0.5 20
23 P0.2
P0.4 21
22 P0.3
MGG020
1997 Dec 12
Fig.2 Pinning configuration for SDIP42.
6

6 Page









P83C280 pdf, datenblatt
Philips Semiconductors
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
Product specification
P83Cx80; P87C380
7.3 Additional Special Function Registers
The standard SFRs as used in 80C51 and the SFRs for some typical derivative functions like I2C-bus interface, Timer,
etc. are described in the “Data Handbook IC20”. The specific SFRs for the P83C880 are introduced in the relevant
chapters. Some SFRs which are not mentioned or not dedicated to a certain function will be described in the following
sections.
All new additional SFRs used in the P83C880 are listed in Table 4. However, only some of them will be explained in detail
in Sections 7.3.1 to 7.3.7.
Table 4 Overview of additional SFRs
REGISTER
DESCRIPTION
ADDRESS RESET VALUE(1) READ/WRITE(2)
RAMBUF
DDCCON
DDCADR
DDCDAT
DFCON
ADCDAT
PWM10H
PWM10L
S1CON
S1STA
S1DAT
S1ADR
PWME1
PWME2
PWM0 to PWM9
DAC0 to DAC3
HFP
HFPOPW
MDCST
VFP
VFPOPW
PULCNT
HFHIGH
VFHIGH
VFLHFL
T2
RAM Buffer I/O Interface Register
9CH
DDC Control Register
9DH
DDC Address Pointer
9EH
Data Shift Register for DDC1
9FH
Miscellaneous Control Register
C0H
ADC Control Register
C1H
PWM High-byte Data Latch
C6H
PWM Low-byte Data Latch
C7H
Control Register for DDC2
D8H
Status Register for DDC2
D9H
Data Shift Register for DDC2
DAH
Address Register for DDC2
DBH
PWM Output Control Register 1
C8H
PWM Output Control Register 2
E8H
Data Latches for 8-bit PWMs
C9H to CFH,
EDH to EFH
8-bit Data Latches for 8-bit DACs
E9H to ECH
Free run Control Register for HSYNCout
F6H
Free run and Pulse width for HSYNCout
Mode Detect Control and Status Register
F7H
F8H
Free run Control Register for VSYNCout
F9H
Free run and Pulse width for VSYNCout
Pulse Generation Control Register
FAH
FBH
Horizontal Period Counting High-byte
Register
FCH
Vertical Period Counting High-byte Register
FDH
Vertical and Horizontal Period Counting
Low-nibbles Register
FEH
Watchdog Timer Data Register
FFH
XXXX XXXX
X00X 0000
0000 0000
0000 0000
1000 0000
XX00 0000
0000 0000
1000 0000
0000 0000
1111 1000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0110 0000
0001 1111
1X00 0000
0100 0000
XX000101
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
B
UBBU BBBB
B
B
B
UUBB BBBRO
B
B
B
Ro
B
B
B
B
B
B
B
B
BUBB RRRR
B
B
B
Ro
Ro
Ro
B
Notes
1. X = don’t care; even if it’s implemented.
2. B = both read/write and Ro = read only; accessible for the entire byte or an individual bit. U = not implemented.
1997 Dec 12
12

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