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P80CE559EBB Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P80CE559EBB
Beschreibung Single-chip 8-bit microcontroller
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
P80CE559EBB Datasheet, Funktion
INTEGRATED CIRCUITS
P83CE559/P80CE559
Single-chip 8-bit microcontroller
Preliminary specification
IC20 Data Handbook
1996 Aug 06
Philips
Semiconductors






P80CE559EBB Datasheet, Funktion
Philips Semiconductors
Single-chip 8-bit microcontroller
Preliminary specification
P83CE559/P80CE559
4.1 PIN DESCRIPTIONS
SYMBOL
PIN
DESCRIPTION
AVref–
AVref+
1
2
Low end of analog to digital conversion reference resistor
High end of analog to digital conversion reference resistor.
AVSS1
AVDD1
3
4
Analog ground for ADC
Analog power supply (+5 V) for ADC
AVSS2
AVDD2
77
76
Analog ground; for PLL oscillator
Analog power supply; (+5 V) for PLL oscillator
P5.7 – P5.0 5 – 12
Port 5
8–bit input port
Port pin
Alternative function
VDD1, VDD2,
VDD3, VDD4
VSS1, VSS2
VSS3, VSS4
ADEXS
14, 28,
53, 66
13, 29,
54, 67
15
PWM0
PWM1
EW
16
17
18
P4.0 – P4.7
19 – 22
24 – 27
RSTIN
RSTOUT
30
23
P1.0 – P1.7 31 – 38
P5.0–P5.7
Eight input channels to ADC (ADC0–ADC7)
Digital power supply: +5 V power supply pins during normal operation and power reduction modes. All pins
must be connected.
Digital ground: circuit ground potential. All pins must be connected.
Start ADC operation: Input starting analog to digital conversion triggered by a programmable edge (ADC
operation can also be started by software). This pin must not float
Pulse width modulation output 0
Pulse width modulation output 1
Enable watchdog timer: Enable for T3 watchdog timer and disable Power–down Mode.This pin must not
float.
Port 4
8–bit quasi–bidirectional I/O port
Port pin
Alternative function
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
CMSR0 }
CMSR1 }
CMSR2 } compare and set/reset
CMSR3 } outputs on a match with timer T2
CMSR4 }
CMSR5 }
CMT0 } compare and toggle outputs
CMT1 } on a match with timer T2
Reset: Input to reset the P8xCE559.
Reset: Output of the P8xCE559 for resetting peripheral devices during initialization and Watchdog Timer
overflow.
Port 1
8–bit quasi–bidirectional I/O port
Port pin
Alternative function
SCL
SDA
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
CT0I/INT2}
CT1I/INT3}
CT2I/INT4}
CT3I/INT5}
T2
RT2
:
:
:
Capture timer inputs for
timer T2 or external interrupt inputs
T2 event input, rising edge triggered
T2 timer reset input, rising edge triggered
39 I2C–bus serial clock I/O port
40 I2C–bus serial data I/O port
If SCL and SDA are not used, they must be connected to VSS.
1996 Aug 06
6

6 Page









P80CE559EBB pdf, datenblatt
Philips Semiconductors
Single-chip 8-bit microcontroller
Preliminary specification
P83CE559/P80CE559
Table 5. Special Function Register Memory Map and Reset Values
High Nibble of SFR Address
LOW
8
9
A
B
C
0 P0 %
P1 %
P2 %
P3 %
P4 %
11111111
11111111
11111111
11111111
11111111
1 SP 00000111
2 DPL
00000000
3 DPH
00000000
4
D
PSW %
00000000
E
ACC %
00000000
F
B%
00000000
5
6
ADRSL0 #
ADRSL1 #
XXXXXXXX XXXXXXXX
7 PCON
00000000
8
TCON %
S0CON %
00000000
00000000
9 TMOD S0BUF
00000000 XXXXXXXX
A TL0
00000000
B TL1
00000000
C TH0
00000000
D TH1
00000000
E
F
%=
#=
X=
*=
Bit addressable register
Read only register
Undefined
FMCON only in P89CE559
ADRSL2 #
XXXXXXXX
IEN0 %
00000000
CML0
00000000
CML1
00000000
CML2
00000000
CTL0 #
XXXXXXXX
CTL1 #
XXXXXXXX
CTL2 #
XXXXXXXX
CTL3 #
XXXXXXXX
ADRSL3 #
XXXXXXXX
IP0 %
X0000000
ADRSL4 #
XXXXXXXX
P5 #
XXXXXXXX
TM2IR %
00000000
CMH0
00000000
CMH1
00000000
CMH2
00000000
CTH0 #
XXXXXXXX
CTH1 #
XXXXXXXX
CTH2 #
XXXXXXXX
CTH3 #
XXXXXXXX
ADRSL5 #
XXXXXXXX
ADCON
00000000
S1CON %
00000000
S1STA #
11111000
S1DAT
00000000
S1ADR
00000000
ADRSL6 #
XXXXXXXX
ADPSS
00000000
IEN1 %
00000000
TM2CON
00000000
CTCON
00000000
TML2 #
00000000
TMH2 #
00000000
STE
11000000
RTE
00000000
ADRSL7 #
XXXXXXXX
ADRSH #
000000XX
IP1 %
00000000
PLLCON
00001101
XRAMP
XXXXX000
FMCON *
000X0000
PWM0
00000000
PWM1
00000000
PWMP
00000000
T3
00000000
6.3 Addressing
The P8xCE559 has five methods for addressing:
Register
Direct
Register–Indirect
Immediate
Base–Register plus Index–Register–Indirect
The first three methods can be used for addressing destination
operands. Most instructions have a “destination/source” field that
specifies the data type, addressing methods and operands involved.
For operations other than MOVs, the destination operand is also a
source operand.
Access to memory addresses is as follows:
Register in one of the four register banks through Register, Direct
or Register–Indirect addressing
1536 bytes of internal RAM through Direct or Register–Indirect
addressing. Bytes 0–127 of internal RAM may be addressed
directly/indirectly. Bytes 128–255 of internal RAM share their
address location with the SFRs and so may only be addressed
indirectly as data RAM. Bytes 0–1279 of AUX–RAM can only be
addressed indirectly via MOVX.
Special Function Register through direct addressing at address
locations 128–255 (see Figure 8).
External data memory through Register–Indirect addressing
Program memory look–up tables through Base– Register plus
Index–Register–Indirect addressing
1996 Aug 06
12

12 Page





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