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P80C592 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P80C592
Beschreibung 8-bit microcontroller with on-chip CAN
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
P80C592 Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
P8xC592
8-bit microcontroller
with on-chip CAN
Product specification
Supersedes data of January 1995
File under Integrated Circuits, IC18
1996 Jun 27






P80C592 Datasheet, Funktion
Philips Semiconductors
8-bit microcontroller with on-chip CAN
Product specification
P8xC592
handbook, full pagewidth
P4.3/CMSR3
P4.4/CMSR4
P4.5/CMSR5
P4.6/CMT0
P4.7/CMT1
RST
P1.0/CT0I/INT2
P1.1/CT1I/INT3
P1.2/CT2I/INT4
P1.3/CT3I/INT5
P1.4/T2
P1.5/RT2
CVSS
P1.6/CTX0
P1.7/CTX1
P3.0/RXD
P3.1/TXD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
P8xC592
60 AVSS
59 AVref
58 AVref
57 CRX0
56 CRX1
55 REF
54 P0.0/AD00
53 P0.1/AD01
52 P0.2/AD02
51 P0.3/AD03
50 P0.4/AD04
49 P0.5/AD05
48 P0.6/AD06
47 P0.7/AD07
46 EA
45 ALE
44 PSEN
MGA148 - 1
1996 Jun 27
Fig.3 Pin configuration PLCC68/SOT188-2 version (P8xC592FFA; FHA;).
6

6 Page









P80C592 pdf, datenblatt
Philips Semiconductors
8-bit microcontroller with on-chip CAN
7.2.1 MAIN RAM
Four 8-bit register banks occupy the lower RAM area,
BANK 0: location 0 to 7
BANK 1: location 8 to 15
BANK 2: location 16 to 23
BANK 4: location 24 to 31.
Only one of these banks may be enabled at the same time.
The next 16 bytes, locations 32 through 45, contains
128 directly addressable bit locations.
The stack can be located anywhere in the internal MAIN
RAM address space. The stack depth is only limited by the
internal RAM space available. All registers except the
program counter and the four 8-bit register banks reside in
the SFR address space.
7.3 External Data Memory
An access to external Data Memory locations higher than
255 will be performed with the MOVX @DPTR instructions
in the same way as in the 80C51 structure,
i.e. with P0 and P2 as data/address bus and P3.6 and P3.7
as Write and Read strobe signals.
Note that these external Data Memory locations cannot be
accessed with R0 or R1 as address pointer.
Product specification
P8xC592
7FH (MSB)
(LSB) 127
2FH
2EH
2DH
2CH
2BH
2AH
29H
28H
27H
26H
25H
24H
23H
22H
21H
20H
1FH
18H
17H
10H
0FH
08H
07H
00H
7F 7E 7D 7C 7B 7A 79 78
77 76 75 74 73 72 71 70
6F 6E 6D 6C 6B 6A 69 68
67 66 65 64 63 62 61 60
5F 5E 5D 5C 5B 5A 59 58
57 56 55 54 53 52 51 50
4F 4E 4D 4C 4B 4A 49 48
47 46 45 44 43 42 41 40
3F 3E 3D 3C 3B 3A 39 38
37 36 35 34 33 32 31 30
2F 2E 2D 2C 2B 2A 29 28
27 26 25 24 23 22 21 20
1F 1E 1D 1C 1B 1A 19 18
17 16 15 14 13 12 11 10
0F 0E 0D 0C 0B 0A 09 08
07 06 05 04 03 02 01 00
BANK 3
BANK 2
BANK 1
BANK 0
MGA152
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
24
23
16
15
8
7
0
Fig.5 Internal MAIN RAM bit addresses.
1996 Jun 27
12

12 Page





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