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P80C554SBBD Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P80C554SBBD
Beschreibung 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless/ 7 channel 10 bit A/D/ I2C/ PWM/ capture/compare/ high I/O/ 64L LQFP
Hersteller NXP Semiconductors
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Gesamt 30 Seiten
P80C554SBBD Datasheet, Funktion
INTEGRATED CIRCUITS
80C554/83C554/87C554
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C,
PWM, capture/compare, high I/O, 64L LQFP
Preliminary specification
Replaces data of 1999 Apr 07
IC20 Data Handbook
2000 Nov 10
Philips
Semiconductors






P80C554SBBD Datasheet, Funktion
Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
PIN DESCRIPTION (Continued)
PIN NO.
MNEMONIC
LQFP TYPE
NAME AND FUNCTION
P4.0-P4.7
14–21
14–19
20, 21
I/O Port 4: 8-bit programmable I/O port. Alternate functions include:
O CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with timer T2.
O CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.
Port 4 has four modes selected on a per bit basis by writing to the P4M1 and P4M2 registers as
follows:
P4M1.x
0
0
1
1
P4M2.x
0
1
0
1
Mode Description
Pseudo-bidirectional (standard c51 configuration; default)
Push-Pull
High impedance
Open drain
P5.0-P5.6
2–8 I Port 5: 8-bit input port.
ADC0-ADC7 (P5.0-P5.7): Alternate function: Seven input channels to the ADC.
RST
22 I/O Reset: Input to reset the 87C554. It also provides a reset pulse as output when timer T3 overflows.
XTAL1
40 I Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal
clock generator. Receives the external clock signal when an external oscillator is used.
XTAL2
39 O Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit when an
external clock is used.
VSS
PSEN
41–42
51
I Digital ground.
O Program Store Enable: Active-low read strobe to external program memory.
ALE/PROG
52 O Address Latch Enable: Latches the low byte of the address during accesses to external memory.
It is activated every six oscillator periods. During an external data memory access, one ALE pulse
is skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external
pull-up. This pin is also the program pulse input (PROG) during EPROM programming.
EA/VPP
53 I External Access: When EA is held at TTL level high, the CPU executes out of the internal program
ROM provided the program counter is less than 16,384. When EA is held at TTL low level, the CPU
executes out of external program memory. EA is not allowed to float. This pin also receives the
12.75 V programming supply voltage (VPP) during EPROM programming.
AVREF–
62 I Analog to Digital Conversion Reference Resistor: Low-end.
AVREF+
63 I Analog to Digital Conversion Reference Resistor: High-end.
AVSS
64 I Analog Ground
AVDD
1 I Analog Power Supply
NOTE:
1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than VDD + 0.5 V or VSS – 0.5 V,
respectively.
2000 Nov 10
6

6 Page









P80C554SBBD pdf, datenblatt
Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
FF
ERAM
256 BYTES
FF FF
UPPER
128 BYTES
INTERNAL RAM
80
SPECIAL
FUNCTION
REGISTER
80
FFFF
EXTERNAL
DATA
MEMORY
LOWER
128 BYTES
INTERNAL RAM
00 00 00
0100
0000
SU00980
Figure 5. Internal and External Data Memory Address Space with EXTRAM = 0
Dual DPTR
The dual DPTR structure (see Figure 6) is a way by which the chip
will specify the address of an external data memory location. There
are two 16-bit DPTR registers that address the external memory,
and a single bit called DPS = AUXR1/bit0 that allows the program
code to switch between them.
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
DPS
BIT0
AUXR1
DPH
(83H)
DPL
(82H)
DPTR1
DPTR0
Figure 6.
EXTERNAL
DATA
MEMORY
SU00745A
Note that bit 2 is not writable and is always read as a zero. This
allows the DPS bit to be quickly toggled simply by executing an
INC AUXR1 instruction without affecting the other bits.
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
INC DPTR
Increments the data pointer by 1
MOV DPTR, #data16 Loads the DPTR with a 16-bit constant
MOV A, @ A+DPTR Move code byte relative to DPTR to ACC
MOVX A, @ DPTR
Move external RAM (16-bit address) to
ACC
MOVX @ DPTR , A
Move ACC to external RAM (16-bit
address)
JMP @ A + DPTR
Jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
2000 Nov 10
12

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