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P80C528IBB Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P80C528IBB
Beschreibung 8-bit microcontrollers
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
P80C528IBB Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
P83C524; P80C528; P83C528
8-bit microcontrollers
Product specification
File under Integrated Circuits, IC20
1997 Dec 15






P80C528IBB Datasheet, Funktion
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frequency
reference
XTAL2
XTAL1
OSCILLATOR
AND
TIMING
PPRROOGGRRAAMM
MMEEMMOORRYY
((3322KKxx88RROOMM/
or 16EPKRxO8MR)OM)
RAM
DATA
MEMORY
(256 x 8 RAM)
AUX - RAM
DATA
MEMORY
(256 x 8 RAM)
counters
T0 T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
T2 T2EX
16-BIT
TIMER
RST
WATCHDOG
TIMER
CPU
internal
interrupts
64K-BYTE BUS
EXPANSION
CONTROL
INT0 INT1
external interrupts
control
P83C524
P80C528
P83C528
PROGRAMMABLE I/O
PROGRAMMABLE
SERIAL PORT
FULL DUPLEX UART
SYNCHRONOUS
SHIFT
BIT-LEVEL
I 2C
INTERFACE
parallel ports,
address/data bus
and I/O pins
serial in
serial out
shared with Port 3
SDA SCL
MBC455
Fig.1 Block diagram.

6 Page









P80C528IBB pdf, datenblatt
Philips Semiconductors
8-bit microcontrollers
Product specification
P83C524; P80C528; P83C528
PIN
SYMBOL
SOT 129-1 SOT 187-2 SOT 307-2
DESCRIPTION
XTAL1 19
VSS 20
P2.0-P2.7 2128
PSEN
29
ALE 30
EA 31
P0.0-P0.7 3239
VDD
40
21
22
2431
(23 n.c.)
32
33
35
(34 n.c.)
3643
44
15
16
1825
(17 n.c.)
26
27
29
(28 n.c.)
3037
38
Crystal input 1: input to the inverting amplifier that forms the
oscillator, and input to the internal clock generator. Receives the
external oscillator clock signal when an external oscillator is used
(see Figures 22 and 23).
Ground: circuit ground potential.
Port 2: 8-bit quasi-bidirectional I/O Port with internal pull-ups.
During access to external memories (RAM/ROM) that use 16-bit
addresses (MOVX @DPTR) Port 2 emits the high-order address
byte (A8 to A15). Port 2 can sink/source one TTL (= 4 LSTTL)
input. It can drive CMOS inputs without external pull-ups.
Program Store Enable output: read strobe to the external
program memory via Port 0 and Port 2. It is activated twice each
machine cycle during fetches from external program memory.
When executing out of external program memory two activations of
PSEN are skipped during each access to external data memory.
PSEN is not activated (remains HIGH) during no fetches from
external program memory. PSEN can sink/source 8 LSTTL inputs.
It can drive CMOS inputs without external pull-ups.
Address Latch Enable output: latches the LOW byte of the
address during access to external memory in normal operation. It
is activated every six oscillator periods except during an external
data memory access. ALE can sink/source 8 LSTTL inputs. It can
drive CMOS inputs without an external pull-up.
External Access input: when during RESET, EA is held at a TTL
HIGH level, the CPU executes out of the internal program ROM,
provided the program counter is less than 32768. When EA is held
at a TTL LOW level during RESET, the CPU executes out of
external program memory via Port 0 and Port 2. EA is not allowed
to float.
Port 0: 8-bit open drain bidirectional I/O Port. It is also the
multiplexed low-order address and data bus during accesses to
external memory (AD0 to AD7). During these accesses internal
pull-ups are activated. Port 0 can sink/source 8 LSTTL inputs.
Power supply: +5 V power supply pin during normal operation,
Idle mode and Power-down mode.
Note
1. To avoid a 'latch-up' effect at power-on, the voltage on any pin (at any time) must not be higher than VDD +0.5 V or
lower than VSS 0.5 V respectively.
1997 Dec 15
12

12 Page





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