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Número de pieza | UPD77113AF1-XXX-CN1 | |
Descripción | MOS INTEGRATED CIRCUIT | |
Fabricantes | NEC | |
Logotipo | ||
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No Preview Available ! DATA SHEET
MOS INTEGRATED CIRCUIT
µPD77113A, 77114
16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS
DESCRIPTION
The µPD77113A and 77114 are 16-bit fixed-point digital signal processors (DSPs).
Compared with the µPD77016 family, these DSPs have improved power consumption and are ideal for battery-
powered mobile terminals such as PDAs and cellular phones.
Both mask ROM and RAM models are available.
For details of the functions of these DSPs, refer to the following User’s Manuals:
µPD77111 Family User’s Manual
: U14623E
µPD77016 Family User’s Manual - Instructions : U13116E
FEATURES
z Instruction cycle (operating clock)
µPD77113A : 13.3 ns MIN (75 MHz MAX)
µPD77114 : 13.3 ns MIN (75 MHz MAX)
z Memory
• Internal instruction memory
µPD77113A : RAM 3.5K words × 32 bits
Mask ROM 48K words × 32 bits
µPD77114 : RAM 3.5K words × 32 bits
Mask ROM 48K words × 32 bits
• Data memory
µPD77113A : RAM 16K words × 16 bits × 2 banks
Mask ROM 32K words × 16 bits × 2 banks
µPD77114 : RAM 16K words × 16 bits × 2 banks
Mask ROM 32K words × 16 bits × 2 banks
External memory space 8K words × 16 bits × 2 banks
ORDERING INFORMATION
Part Number
µPD77113AF1-xxx-CN1
µPD77114GC-xxx-9EU
Package
80-pin plastic fine-pitch BGA (9 × 9)
100-pin plastic TQFP (fine pitch) (14 × 14)
Remark xxx indicates ROM code suffix.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14373EJ3V0DS00 (3rd edition)
Date Published February 2001 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1999
1 page µPD77113A, 77114
PIN CONFIGURATION
80-pin plastic fine-pitch BGA (9 × 9)
µPD77113AF1-xxx-CN1
(Bottom View)
9
8
7
6
5
4
3
2
1
J HGFE DCB A
(Top View)
ABCDE FGHJ
Index mark
Pin No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
Pin Name
−
NU
EVDD
INT3
GND
TMS
GND
TRST
−
NU
NU
INT1
INT4/WAKEUPNote
IVDD
TICE
IVDD
HA1
CLKOUT
GND
NU
Pin No.
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
E1
E2
E3
E4
Pin Name
NU
RESET
TDI
TDO
CLKIN
HA0
EVDD
EVDD
NU
INT2
NU
TCK
GND
HWR
HRD
EVDD
NU
GND
SIAK1
NU
Pin No.
E6
E7
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
Pin Name
HCS
GND
HD1
HD2
NU
NU
SOEN1
GND
HD0
SI2
HD3
HD6
HD5
EVDD
GND
SIEN1
SO1
IVDD
HD4
P2
Pin No.
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
J1
J2
J3
J4
J5
J6
J7
J8
J9
Pin Name
P1
GND
NU
NU
SCK1
SOEN2
SIEN2
P3
P0
HD7
NU
−
NU
SI1
SORQ1
SO2
SCK2
EVDD
NU
−
Note The function of the WAKEUP pin can be activated or deactivated by a mask option.
Data Sheet U14373EJ3V0DS
5
5 Page µPD77113A, 77114
• External data memory interface (µPD77114 only)
Pin Name
X/Y
Pin No.
100-pin TQFP 80-pin BGA
99 −
DA0 - DA12 16 - 4
−
D0 - D15
34 - 27, 24 - 17
MRD
97
MWR
96
HOLDRQ
92
−
−
−
−
BSTB
94
HOLDAK
93
−
−
I/O
Function
Shared by:
Output
(3S)
Output
(3S)
I/O
(3S)
Output
(3S)
Output
(3S)
Input
Output
Output
Memory select signal output.
0: Uses X memory.
1: Uses Y memory.
Address bus of external data memory.
• Accesses the external memory.
• Continuously outputs the external memory
address accessed last when the external
memory is not being accessed. Kept low
(0x000) if the external memory is never
accessed after reset.
16-bit data bus.
• Accesses the external memory.
Read output
• External memory read
Write output
• External memory write
Hold request signal
• Input a low level to this pin when the external
device uses the external data memory bus of
the µPD77114.
Bus strobe signal
• This pin goes low when the µPD77114 uses
the external data memory bus.
Hold acknowledge signal
• This pin goes low when the external device
is enabled to use the external data memory
bus of the µPD77114.
−
−
−
−
−
−
−
−
Remark Pins marked “3S” under the heading “I/O” go into a high-impedance state in the following conditions:
X/Y, DA0-DA12, MRD, MWR: When the bus is released (HOLDAK = low level)
D0-D15: When the external data memory is not being accessed and when the bus is released
(HOLDAK = low level)
Data Sheet U14373EJ3V0DS
11
11 Page |
Páginas | Total 30 Páginas | |
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