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DS4302Z-020 Schematic ( PDF Datasheet ) - Maxim Integrated Products

Teilenummer DS4302Z-020
Beschreibung 2-Wire/ 5-Bit DAC with Three Digital Outputs
Hersteller Maxim Integrated Products
Logo Maxim Integrated Products Logo 




Gesamt 8 Seiten
DS4302Z-020 Datasheet, Funktion
Rev 1; 6/04
2-Wire, 5-Bit DAC with Three Digital Outputs
General Description
The DS4302 is a 5-bit digital-to-analog converter (DAC)
with three programmable digital outputs. The DS4302
communicates through a 2-wire, SMBus™-compatible,
serial interface. The tiny 8-pin µSOP package is ideal
for use in space-constrained applications.
Features
SO Package is a Drop-In Replacement for the
MPS1251 and MPS1252
Single 5-Bit DAC (32 Steps)
0V to 2V and 0V to 1.9V Versions
Three Programmable Digital Outputs
SMBus-Compatible Serial Interface
4.5V to 5.5V Supply Voltage Range
8-Pin SO and 8-Pin µSOP Packages
Industrial Temperature Range: -40°C to +85°C
Applications
CCFL Backlight Brightness Control
Power-Supply Calibration
Ordering Information
PART
VOUT
RANGE
TOP
BRAND
DS4302Z-020
DS4302Z-019*
DS4302U-020
DS4302U-019*
0V to 2.0V
0V to 1.9V
0V to 2.0V
0V to 1.9V
4302B
4302A
4302B
4302A
Add “/T&R” for tape-and-reel orders.
*Contact factory for availability.
PIN-
PACKAGE
8 SO
8 SO
8 µSOP
8 µSOP
Pin Description
PIN NAME
FUNCTION
1 SCL Serial Clock Input. 2-wire clock input.
2
SDA
Serial Data Input/Output. Bidirectional,
2-wire data pin.
3 VOUT DAC Output Voltage
4 GND Ground
5 P2
6 P1 Programmable Digital Output
7 P0
8 VCC Power-Supply Input
SMBus is a trademark of Intel Corp.
Pin Configuration
TOP VIEW
SCL 1
SDA 2
VOUT 3
GND 4
DS4302
8 VCC
7 P0
6 P1
5 P2
SO/µSOP
______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.






DS4302Z-020 Datasheet, Funktion
2-Wire, 5-Bit DAC with Three Digital Outputs
DATA BYTE
DAC VALUE
MSB
P2 P1 P0
Figure 1. Data Byte Configuration
Detailed Description
The DS4302 contains a 5-bit DAC and three programma-
ble digital outputs. The DAC setting and the pro-
grammed output levels are contained in a 1-byte data
word that defaults to 00h on power-up (see Figure 1 for
data byte configuration). The upper 5 MSbits of the byte
set the DAC and control the voltage produced on VOUT.
A setting of 1111 1XXX sets the minimum output voltage
from the DAC while a setting of 0000 0XXX sets the maxi-
mum output voltage from the DAC. The three LSbits of
the data byte control the three output pins, P0, P1, and
P2. Setting any of these control bits to a 0 pulls the corre-
sponding outputs low and setting the bits to a 1 pulls the
outputs high.
The DS4302 communicates through a 2-wire (SMBus-
compatible) digital interface and has a 2-wire address of
58h. Write and read operations are used to access the
DAC and output settings. Each operation begins with a
2-wire START condition, consists of three bytes, and
ends with a 2-wire STOP condition (see Figure 2). Using
the write operation, the 2-wire master can program the
5-bit DAC to adjust the voltage on VOUT and set the
level of the three output pins: P0, P1, and P2. The read
operation is used to recall the programmed settings.
2-Wire Definitions
The following terminology is commonly used to
describe 2-wire data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, START, and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle, it initiates a
low-power mode for slave devices.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See Figure 3 for
applicable timing.
STOP Condition: A STOP condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a STOP condition. See Figure 3 for applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements (see Figure 3). Data is
shifted into the device during the rising edge of the SCL.
COMMUNICATIONS KEY
S START
A ACK
P STOP
WHITE BOXES INDICATE THE MASTER IS
CONTROLLING SDA
SHADED BOXES INDICATE THE SLAVE IS
CONTROLLING SDA
X X X X X X X X 8-BITS ADDRESS OR DATA
WRITE A SINGLE BYTE 58h
S 01011000
AAh
A 10101010
A
READ A SINGLE BYTE 59h
00h
S 01011001 A 00000000 A
Figure 2. 2-Wire Communication Examples
DATA BYTE
DATA BYTE
NOTES:
1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.
2) THE FIRST BYTE SENT AFTER A START CONDITION IS
ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE
READ/WRITE BIT.
AP
AP
6 _____________________________________________________________________

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