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Número de pieza | SAA7188 | |
Descripción | Digital Video Encoder DENC2-M | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de SAA7188 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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DATA SHEET
SAA7188A
Digital Video Encoder (DENC2-M)
Preliminary specification
Supersedes data of 1995 Sep 21
File under Integrated Circuits, IC22
1996 Jul 08
1 page Philips Semiconductors
Digital Video Encoder (DENC2-M)
Preliminary specification
SAA7188A
SYMBOL
LLC
CREF
XTALO
XTALI
VSSD6
RTCI
AP
SP
VrefL
VrefH
VDDA1
CHROMA
VDDA2
Y
VSSA
CVBS
VDDA3
II
VDDA4
RESET
DTACK
RW/SCL
A0/SDA
CS/SA
VSSD7
DP0
DP1
DP2
DP3
VDDD3
SEL_MPU
PIN DESCRIPTION
38 Line-Locked Clock. This is the 27 MHz master clock for the encoder. The direction is set by
the CDIR pin.
39 Clock Reference signal. This is the clock qualifier for DIG-TV2 compatible signals.
40 Crystal oscillator output (to crystal).
41 Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be connected
to ground.
42 digital ground 6
43 Real Time Control Input. If the clock is provided by an SAA7151B, RTCI should be connected
to the RTCO pin of the decoder to improve the signal quality.
44 Test pin. Connect to digital ground for normal operation.
45 Test pin. Connect to digital ground for normal operation.
46 Lower reference voltage input for the DACs.
47 Upper reference voltage input for the DACs.
48 Analog positive supply voltage 1 for the DACs and output amplifiers.
49 Analog output of the chrominance signal.
50 Analog supply voltage 2 for the DACs and output amplifiers.
51 Analog output of the luminance signal.
52 Analog ground for the DACs and output amplifiers.
53 Analog output of the CVBS signal.
54 Analog supply voltage 3 for the DACs and output amplifiers.
55 Current input for the output amplifiers, connect via a 15 kΩ resistor to VDDA.
56 Analog supply voltage 4 for the DACs and output amplifiers.
57 Reset input, active LOW. After reset is applied, all outputs are in 3-state input mode.
The I2C-bus receiver waits for the start condition.
58 Data acknowledge output of the parallel MPU interface, active LOW, otherwise high
impedance.
59 If pin 68 (SEL_MPU) is HIGH, this is the read/write signal of the parallel MPU interface,
otherwise it is the I2C-bus serial clock input.
60 If pin 68 (SEL_MPU) is HIGH, this is the address signal of the parallel MPU interface,
otherwise it is the I2C-bus serial data input/output.
61 If pin 68 (SEL_MPU) is HIGH, this is the chip select signal of the parallel MPU interface,
otherwise it is the I2C-bus slave address select pin. LOW: slave address = 88h, HIGH = 8Ch.
62 digital ground 7
63
64 Lower 4 bits of the Data Port. If pin 68 (SEL_MPU) is HIGH, this is the data bus of the parallel
65 MPU interface. If it is LOW, they are the UV lines of the Video Port.
66
67 digital supply voltage 3
68 Select MPU interface input. If it is HIGH, the parallel MPU interface is active, otherwise the
I2C-bus interface will be used.
1996 Jul 08
5
5 Page Philips Semiconductors
Digital Video Encoder (DENC2-M)
Preliminary specification
SAA7188A
1996 Jul 08
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet SAA7188.PDF ] |
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