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Número de pieza | S6A0072 | |
Descripción | 16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER | |
Fabricantes | Samsung semiconductor | |
Logotipo | ||
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No Preview Available ! 16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
INTRODUCTION
S6A0072 is a dot matrix LCD driver & controller IC which is fabricated by low power CMOS technology. It is
capable of displaying 1-line 16 characters or 2-line 8 characters with 5 × 8 dots format.
FUNCTIONS
Character type dot matrix LCD driver & controller
• Easy interface with 4-bit or 8-bit MPU.
• Internal driver: 16 common and 40 segment signal output.
• Display character pattern: 5 × 8 dots format (240 kinds)
• Direct programming of the special character patterns by character generator RAM
• Mask option for programming customer character patterns
• Various instruction functions
• Automatic power on reset
FEATURES
• Internal Memory
- Character Generator ROM (CGROM): 9600 bits (240 characters × 5 × 8 dot)
- Character Generator RAM (CGRAM): 160 bits (4 characters × 5 × 8 dot)
- Display Data RAM (DDRAM): 128 bits (16 characters × 8bits)
• Low power operation
- Power supply voltage range: 2.7 to 5.5V (VDD)
- LCD drive voltage range: 3.0 to 11.0 (VDD-V5)
• CMOS process
• Duty cycle: 1/16
• Built-in oscillator
• Low power consumption
• Internal divide resistor for LCD driving voltage
• COG available
1
1 page 16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
PIN DESCRIPTION
Pin Input/Output
Name
Description
Interface
VDD
Power
Power supply & for logical circuit (+3V, +5V)
LCD bias pin
Power supply
VSS (GND)
V2, V3, V5
S1 - S40
C1 - C16
EXTCLK
EXT_INT
RS
R/W
E
DB0-DB3
DB4-DB7
RESETB
TEST
Output
Input
Input
Input
Input
Input
Input
Input/Output
Input
Output
Segment output
Common output
External clock
Input
External/internal
oscillator clock
select
Register select
Read/write
Read/write
enable
Data bus 0 - 7
Reset
Test pin
0V (GND)
Bias voltage level for LCD driving
Segment signal output for LCD driving
Common signal output for LCD driving
When using external clock, used as clock
input pin. When using internal oscillator,
connect to VDD or VSS.
When EXT_INT = "High", external clock is
used. When "Low", internal oscillator is used.
Used as register selection input.
When RS = "High", Data register is selected.
When RS = "Low", Instruction register is
selected.
Used as read/write selection input.
When R/W = "High", read operation.
When R/W = "Low", write operation.
Used as read/write enable signal.
When 8-bit bus mode, used as low order
bi-directional data bus.
During 4-bit bus mode open these pins.
When 8-bit bus mode, used as high order bi-
directional data bus. In case of 4-bit bus
mode, used as both high and low order.
DB7 is used for busy flag output during read
instruction operation.
If it is necessary to initialize the system by
hardware, force "Low", level signal to this
terminal about 1.2ms.
Internal oscillator test pin. Open this pin.
LCD
LCD
External clock
VDD/VSS
MPU
Open
5
5 Page 16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
Table 3. Instruction Table
Instruction
Test mode
Clear display
Return home
Entry mode set
Display ON/OFF
control
Cursor or display
shift
Function set
Set CGRAM
address
Set DDRAM
address
Read
busy
flag
and
DDRAM
Instruction Code
Description
Execution
Time
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(fosc =
270kHz)
0 0 0 0 0 0 0 0 0 0 Device test mode
(When 4-bit interface mode)
No operation
(When 8-bit interface mode)
-
0 0 0 0 0 0 0 0 0 1 Write "20H" to DDRAM and
set DDRAM address to
"00H" from AC.
631µs
000000001
* Set DDRAM address to
"00H" from AC and return
cursor to its original position
if shifted.
The contents of DDRAM are
not changed.
631µs
0 0 0 0 0 0 0 1 I/D S Assign cursor moving
direction and enable entire
display shift.
39µs
0 0 0 0 0 0 1 D C B All display (D), cursor (C),
and blinking of cursor
position character on/off
control bit (B).
39µs
0 0 0 0 0 1 S/C R/L *
* Cursor and display shift and
their direction control without
changing DDRAM data.
39µs
0 0 0 0 1 DL A * M1 M0 Set interface data length
(DL), DDRAM addressing
mode (A) and COM/SEG
output pattern (M0, M1).
39µs
0 0 0 1 * AC4 AC3 AC2 AC1 AC0 Set CGRAM address in
address counter.
39µs
0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in
address counter.
39µs
0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 Whether in internal operation
or not can be known by
reading BF. The contents of
address counter can also be
0µs
Add- CGRAM
ress
* * AC4 AC3 AC2 AC1 AC0 read
Note: “*” don’t care.
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet S6A0072.PDF ] |
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