EM84530 Datasheet PDF - ELAN Microelectronics Corp
| Part Number | EM84530 | |
| Description | 2-IN-ONE MOUSE CONTROLLER | |
| Manufacturers | ELAN Microelectronics Corp | |
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There is a preview and EM84530 download ( pdf file ) link at the bottom of this page. Total 14 Pages | ||
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Preliminary
EM84530
2-IN-ONE MOUSE CONTROLLER
GENERAL DESCRIPTION
The EM84530 Mouse Controller is specially designed to control serial mouse or PS/2 mouse device.
This single chip can interface three key-switches and 4 X-Y photo-couples directly to RS-232C or 8042
controller.
FEATURES
• Include PnP software scrolling function
• Using 50kΩ ±1% resistor for RC oscillation.
• Compatible with legacy PS/2 mouse.
• Compatible with Microsoft serial mouse.
• Compatible with Microsoft PS/2 mouse.
• Serial or PS/2 port auto-detect.
• 100 bytes PnP ID code could be filled by code layer.
• Built-in noise immunity circuit.
• The sampiling rate of motion detector is up to 65KHz.
• Built-in three zener diodes : one in VDD to VSS, two in RTS to VDD.
• CMOS push-pull RXD output.
• Built-in current comparator for photo-couples input.
• Built-in three step dynamic input impedance.
• Three key-switches and four photo-couples inputs.
• RTS debouncing circuit included.
• Photo couple test mode included.
• Low power dissipation.
APPLICATION
• Serial PnP mouse.
• PS/2 mouse.
• Combo mouse.
PIN ASSIGNMENT
EM84530
VDD
OSC.OUT
NC
NC
CLK/RTS
DATA/RXD
OPT
VSS
1
2
3
4
5
6
7
8
16 OSCR
15 Y2
14 Y1
13 X2
12 X1
11 L
10 M
9R
* This specification are subject to be changed without notice.
6.28.1999 1
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c). Data transmission frame:
Preliminary
EM84530
2-IN-ONE MOUSE CONTROLLER
Bit Function
1 Start bit ( always 0 )
2-9 Data bits ( D0 - D7 )
10 Parity bit ( odd parity )
11 Stop bit ( always 1 )
d). Data Output ( data from EM84530 to system ):
If CLK is low ( inhibit status ) , data is no transmission.
If CLK is high and DATA is low ( request-to-send ), data is updated. Data is received from the system
and no transmission are started by EM84530 until CLK and DATA both high. If CLK and DATA both
are high, the transmission is ready. DATA is valid prior to the falling edge of CLK and beyond the rising edge
of CLK. During transmission, EM84530 check for line contention by checking for an inactive level on CLK
at intervals not to exceed 100u sec. Contention occurs when the system lowers CLK to inhibit EM84530
output after EM84530 has started a transmission. If this occurs before the rising edge of the tenth clock,
EM84530 internal store its data in its buffer and returns DATA and CLK to an active level. If the contention
does not occur by the tenth clock, the transmission is complete.
Following a transmission, the system inhibits EM84530 by holding CLK low until it can service the input
or until the system receives a request to send a response from EM84530.
e). Data Input ( from system to EM84530 ):
The system first check if EM84530 is transmitting data. If EM84530 is transmitting, the system can override
the output forcing CLK to an inactive level prior to the tenth clock. If EM84530 transmission is beyond
the tenth clock, the system receives the data. If EM84530 is not transmitting or if the system choose to
override the output, the system force CLK to an inactive level for a period of not less than 100µ sec while
preparing for output. When the system is ready to output start bit (0), it allows CLK go to active level. If
request-to-send is detected, EM84530 clocks 11 bits. Following the tenth clock EM84530 checks for
an active level on the DATA line, and if found, force DATA low , and clock once more. If occurs framing
error, EM84530 continue to clock until DATA is high, then clocks the line control bit and request a
Resend. When the system sends out a command or data transmission that requires a response, the system
waits for EM84530 to response before sending its next output.
D). PS/2 Mouse Error Handling:
a). A Resend command ( FE ) following receipt of an invalid input or any input with incorrect parity.
b). If two invalid input are received in succession, an error code of hex (FC) is send to the system.
c). The counter accumulators are cleared after receiving any command except “Resend”.
d). EM84530 receives a Resend command ( FE ), it transmit its last packet of data.
e). In the stream mode “Resend” is received by EM84530 following a 3-byte data packet transmission
to the system. EM84530 resend the 3-byte data packet prior to clearing the counter.
* This specification are subject to be changed without notice.
6.28.1999 5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for EM84530 electronic component. |
| Information | Total 14 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ EM84530.PDF Datasheet ] | |
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