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EM78P860 Schematic ( PDF Datasheet ) - ELAN Microelectronics Corp

Teilenummer EM78P860
Beschreibung 8 -BIT MICRO-CONTROLLER
Hersteller ELAN Microelectronics Corp
Logo ELAN Microelectronics Corp Logo 




Gesamt 26 Seiten
EM78P860 Datasheet, Funktion
EM78P860
8 -BIT MICRO-CONTROLLER
I. GENERAL DESCRIPTION
The EM78P860 is an 8-bit RISC type microprocessor with low power , high speed CMOS technology .
Integrated onto a single chip are on_chip watchdog (WDT) , RAM , ROM , programmable real time clock /counter ,
internal interrupt , power down mode , LCD driver and tri-state I/O . The EM78P860 provides a single chip solution
to design a message display .
II. FEATURES
CPU
• Operating voltage range : 2.5V~5.5V
• 16Kx13 on chip ROM
• 2.8Kx8 on chip RAM
• Up to 32 bi-directional tri-state I/O ports
• 8 Level stack for subroutine nesting
• 8-bit real time clock/counter (TCC)
• Two sets of 8 bit counters can be interrupt sources
• Selective signal sources and with overflow interrupt
• Programmable free running on chip watchdog timer
• 99.9% single instruction cycle commands
• Four modes (internal clock 3.679MHz, external 32.768KHz)
1. Sleep mode : CPU and 3.679MHz clock turn off, 32.768KHz clock turn off
2. Idle mode : CPU and 3.679MHz clock turn off, 32.768KHz clock turn on
3. Green mode : 3.679MHz clock turn off, CPU and 32.768KHz clock turn on
4. Normal mode : 3.679MHz clock turn on , CPU and 32.768KHz clock turn on
• Low battery detector
• Input port wake up function
• 8 interrupt source , 4 external , 3 internal
100 pin QFP (EM78860AQ, POVD disable) (EM78860BQ, POVD enable) or chip (EM78860H)
• Port key scan function
• Port interrupt , pull high and open drain functions
• Clock frequency 32.768KHz externally
LCD
• LCD operation voltage chosen by software
• Common driver pins : 16
• Segment driver pins : 60
• 1/4 bias
• 1/8,1/16 duty
III. APPLICATION
1. adjunct units
* This specification is subject to be changed without notice.
4.17.2000 1






EM78P860 Datasheet, Funktion
EM78P860
8 -BIT MICRO-CONTROLLER
5. R4 ( RAM Select Register )
• Bit 0 ~ 5 are used to select up to 64 register in the indirect addressing mode.
• Bit 6 ~ 7 determine which bank is actived among the 4 banks.
• See the configuration of the data memory in Fig. 4.
6. R5 ( Program Page Select Register)
7 6 54 3 21
0
-
-
-
-
PS3 PS2 PS1
PS0
• Bit 0 (pS0) ~ 3 (PS3) Page selec bits.
Page select bits
PS3 PS2 PS1 PS0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
program memory page (Address)
Page 0
Page 1
Page 2
Page 3
Page 4
page 5
Page 6
Page 7
Page 8
Page 9
Page 10
Page 11
Page 12
Page 13
Page 14
Page 15
• User can use PAGE instruction to change page. To maintain program page by user. Otherwise, user can use
far jump (FJMP) or far call (FCALL) instructions to program user's code. And the program page is maintained
by EMC's complier. It will change user's program by inserting instruction within program.
• Bit4~7 : unused
7. R6 ~R9 ( Port 6 ~ Port 9)
• Five 8-bit I/O registers.
8. RA
7
IDLE
6
/358E
5
/LPD
4
/LOW-BAT
3
0
21
00
0
0
• Bit0 ~ Bit3 unused, please set to "0"
* This specification is subject to be changed without notice.
4.17.2000 6

6 Page









EM78P860 pdf, datenblatt
EM78P860
8 -BIT MICRO-CONTROLLER
Bit 1 : zero
• Bit 2~4 (Bias1~Bias3) Control bits used to choose LCD operation voltage .
LCD operate voltage
000
001
010
011
100
101
110
111
Vop (VDD 5V)
0.60VDD
0.66VDD
0.74VDD
0.82VDD
0.87VDD
0.93VDD
0.96VDD
1.00VDD
VDD=5V
3.0V
3.3V
3.7V
4.0V
4.4V
4.7V
4.8V
5.0V
• Bit5:port6 switch , 0/1= normal I/O port/COMMON output
• Bit6:port9 low nibble switch , 0/1= normal I/O port/SEGMENT output . Bit7:port9 high nibble switch
PAGE1 :
7 6 54 3 2
OP77
OP76
C2S
C1S
PSC1
PSC0
1
-
0
-
• Bit0: unused, please set to ‘0’
• Bit1: unused, please set to ‘0‘
• Bit3~Bit2: counter1 prescaler , reset=(0,0)
(PSC1,PSC0) = (0,0)=>1:1 , (0,1)=>1:2 , (1,0)=>1:4 , (1,1)=>1:8
• Bit4:counter1 source , (0/1)=(32768Hz/3.679MHz if enable)
• Bit5:counter2 source , (0/1)=(32768Hz/3.679MHz if enable) scale=1:1
• Bit6:P76 opendrain control (0/1)=(disable/enable)
• Bit7:P77 opendrain control (0/1)=(disable/enable)
9. IOCF (Interrupt Mask Register)
7 6 54 3 21
0
INT3
-
C8_2
C8_1
INT2
INT1
INT0
TCIF
• Bit 0 ~ 7 interrupt enable bit.
0: disable interrupt
1: enable interrupt
• IOCF Register is readable and writable.
It is very important to save ACC,R3 and R5 when processing a interruption.
Address
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
:
:
:
:
:
:
:
:
Instruction
DISI
MOV A_BUFFER,A
SWAP A_BUFFER
SWAPA 0x03
MOV R3_BUFFER,A
MOV A,0x05
MOV R5_BUFFER,A
:
:
MOV A,R5_BUFFER
MOV 0X05,A
SWAPA R3_BUFFER
MOV 0X03,A
SWAPA A_BUFFER
RETI
Note
;Disable interrupt
;Save ACC
;Save R3 status
;Save ROM page register
;Return R5
;Return R3
;Return ACC
* This specification is subject to be changed without notice.
4.17.2000 12

12 Page





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