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EM78P447S Schematic ( PDF Datasheet ) - ELAN Microelectronics Corp

Teilenummer EM78P447S
Beschreibung 8-bit microprocessor with low-power and high-speed CMOS technology
Hersteller ELAN Microelectronics Corp
Logo ELAN Microelectronics Corp Logo 




Gesamt 27 Seiten
EM78P447S Datasheet, Funktion
EM78P447S
I. GENERAL DESCRIPTION
EM78P447S is an 8-bit microprocessor with low-power and high-speed CMOS technology. There is a 4096*13-
bit Electrical One Time Programmable Read Only Memory (OTP-ROM) within it. It provides a PROTECTION
bit to prevent a user’s code from intruding as well as 8 other OPTION bits to match the user’s requirements.
Because of the OTP-ROM, the EM78P447S offers users a convenient way to develop and verify their programs.
Moreover, a user’s developed code can be programmed easily by an EMC writer.
II. FEATURES
• Operating voltage range: 2.2V~5.5V
• Available in temperature range: 0°C~70°C
• Operating frequency range: DC ~ 20MHz
• Low power consumption:
* less than 2.2 mA at 5V/4MHz
* typical of 30µA at 3V/32KHz
* typical of 1µA during the sleep mode
• 4096 x 13 bits on chip ROM
• 148 x 8 bits on chip registers (SRAM)
• 3 bi-directional I/O ports
• 5 level stacks for subroutine and interrupt
• 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt
• Power-down mode (SLEEP mode)
• Two available interruptions
* TCC overflow interrupt
* External interrupt(INT pin)
• Programmable free running watchdog timer
• 10 programmable pull-high I/O pins
• 2 programmable R-option I/O pins
• 2 programmable open-drain I/O pins
• Two clocks per instruction cycle
• 99.9% single instruction cycle commands
• Package type:
* 28 pin DIP and SOIC
(EM78P447SA)
* 32 pin DIP and SOIC
(EM78P447SB)
* This specification is subject to be changed without notice. 12.29.1999
B3-1






EM78P447S Datasheet, Funktion
EM78P447S
PS1 PS0
00
01
10
11
Program memory page [Address]
Page 0 [000-3FF]
Page 1 [400-7FF]
Page 2 [800-BFF]
Page 3 [C00-FFF]
• Bit 7(GP)
General read/write bit.
5. R4 (RAM Select Register)
• Bits 0~5 are used to select registers (address: 00~3F) in the indirect addressing mode.
• Bit 6~7 are used to select bank 0 ~ 4.
• See the configuration of the data memory in Fig. 4.
6. R5 ~ R7 (Port 5 ~ Port 7)
• R5, R6 and R7 are I/O registers.
7. R8~R1F, R20~R3E(General-purpose Register)
• R8~R1F and R20~R3E (including Bank 0~3) are general-purpose registers.
8. R3F (Interrupt Status Register)
76
--
5 43210
-
- EXIF -
- TCIF
• Bit 0 (TCIF) TCC overflowing interrupt flag. Set when TCC overflows, reset by software.
• Bit 3 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software.
• Bits1~2 and 4~7 Not used.
• “1” means interrupt request, and “0” means non-interrupt occurrence.
• R3F can be cleared by instruction but can not be set.
• IOCF is the interrupt control register.
• Note that the result of reading R3F is the “logic AND” of R3F and IOCF.
* This specification is subject to be changed without notice. 12.29.1999
B3-6

6 Page









EM78P447S pdf, datenblatt
EM78P447S
VCC
Weekly
Pull-up
ROC
PCRD
Q PR D
CLK
Q CL
PCWR
PORT
Rex*
0M
1U
X
Q PR D
CLK
Q CL
PDWR
PDRD
* The Rex is 560K ohm external resistor
Fig. 7(b) The circuit of I/O port with R-option (P70,P71)
IOD
Oscillator
VDD
DQ
CLK
CLR
CLK
Power-on
Reset
WTE
WDT WDT Timeout
18 ms
Reset
RESET
VI.5 RESET and Wake-up
Fig. 8 Block diagram of Reset of controller
1. RESET
The RESET can be caused by
(1) Power-on reset,
(2) /RESET pin input “low”, or
(3) WDT timeout. (if enabled)
* This specification is subject to be changed without notice. 12.29.1999
B3-12

12 Page





SeitenGesamt 27 Seiten
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