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EM78P156E Schematic ( PDF Datasheet ) - ELAN Microelectronics Corp

Teilenummer EM78P156E
Beschreibung 8-bit microprocessor with low-power and high-speed CMOS technology
Hersteller ELAN Microelectronics Corp
Logo ELAN Microelectronics Corp Logo 




Gesamt 28 Seiten
EM78P156E Datasheet, Funktion
EM78P156E
I. GENERAL DESCRIPTION
EM78P156E is an 8-bit microprocessor with low-power and high-speed CMOS technology. There is a 1K*13-
bit Electrical One Time Programmable Read Only Memory (OTP-ROM) within it. It provides a PROTECTION
bit to prevent a user’s code from intruding as well as 7 OPTION bits to match the user’s requirements.
Because of the OTP-ROM, the EM78P156E offers users a convenient way to develop and verify their programs.
Moreover, a user’s developed code can be programmed easily by an EMC writer.
II. FEATURES
• Operating voltage range: 2.2V~5.5V
• Available in temperature range: 0°C~70°C
• Operating frequency range: DC ~ 36MHz
• Low power consumption:
* less than 1.6 mA at 5V/4MHz
* typical of 15 µA at 3V/32KHz
* typical of 1 µA during the sleep mode
• 1Kx13 bits on chip ROM
• One security register to prevent the code in the OTP memory from intruding
• One configuration register to match the user’s requirements
• 48x8 bits on chip registers (SRAM)
• 2 bi-directional I/O ports
• 5 level stacks for subroutine nesting
• 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt
• Two clocks per instruction cycle
• Power-down mode (SLEEP mode)
• Three available interruptions
* TCC overflow interrupt
* Input-port status changed interrupt (wake up from the sleep mode)
* External interrupt
• Programmable free running watchdog timer
• 8 pull-high pins
• 7 pull-down pins
• 8 open-drain pins
• Two R-option pins
• Package type: SOP, SOIC and DIP
• 99.9% single instruction cycle commands
* This specification is subject to be changed without notice. 8.11.1999
B3-1






EM78P156E Datasheet, Funktion
EM78P156E
• Internal data transfer, or instruction operand holding
• It can not be addressed.
2. CONT (Control Register)
76
543
2
-
/INT
TS
TE PAB PSR2
Bit 0 (PSR0)~Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2
0
0
0
0
1
1
1
1
PSR1
0
0
1
1
0
0
1
1
PSR0
0
1
0
1
0
1
0
1
TCC Rate
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
1
PSR1
0
PSR0
WDT Rate
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
Bit 4 (TE) TCC signal edge
0: increment if the transition from high to low takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin
Bit 5 (TS) TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin
Bit 6 (INT) Interrupt enable flag
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instruction
• CONT register is both readable and writable.
3. IOC5 ~ IOC6 (I/O Port Control Register)
• “1” puts the relative I/O pin into high impedance, while “0” defines the relative I/O pin as output.
• Only the lower 4 bits of IOC5 are able to be defined.
• IOC5 and IOC6 registers are both readable and writable.
4. IOCA (Prescaler Counter Register)
• IOCA register is readable.
• The value of IOCA is equal to the contents of Prescaler counter.
• Down counter.
* This specification is subject to be changed without notice. 8.11.1999
B3-6

6 Page









EM78P156E pdf, datenblatt
EM78P156E
Table 2 Usage of Port 6 input changed wake-up/interrupt function
Usage of Port 6 Input Status Changed Wake-up/Interrupt
(I) Wake-up from Port 6 input status changed
(II) Port 6 input status changed Interrupt
(a) Before SLEEP
1. Disable WDT1 (using very carefully)
1. Read I/O Port 6 (MOV R6,R6)
2. Execute "ENI"
2. Read I/O Port 6 (MOV R6,R6)
3. Enable interrupt (Set IOCF.1)
3. Execute "ENI" or "DISI"
4. Enable interrupt (Set IOCF.1)
5. Execute “SLEP” instruction
4. If Port 6 changed (interrupt)
Interrupt vector (008H)
(b) After wake-up
1. If "ENI" Interrupt vector (008H)
2. If "DISI" Next instruction
1 Note : Software disables WDT (watchdog timer) but hardware must be enabled before using port6 changed
wake-up function. (CODE Option Register, bit 11 (ENWDTB-) set to "1").
VCC
ROC
PCRD
Weekly
Pull-up
Q
P
R
D
CLK
Q
C
L
PCWR
PORT
Rex *
0M
1U
X
Q
P
R
D
CLK
Q
C
L
PDWR
PDRD
IOD
* The Rex is 430K ohm external resistor.
Fig. 8 The circuit of I/O port with R-option (P50,P51)
VI.5 RESET and Wake-up
1. RESET
The RESET can be caused by
(1) Power-on reset
(2) /RESET pin input "low", or
(3) WDT time-out (if enabled).
Note that only power-on reset, or only voltage detector in Case (1) is enabled in the system by CODE option bit.
Refer to Fig. 9. The device will be kept in a RESET condition for a period of approx. 18ms (one-oscillator start-
up timer period) after the reset is detected. Once the RESET occurs, the following functions
are performed.
• The oscillator is running, or will be started.
• The Program Counter (R2) is set to all "0".
• All I/O port pins are configured as input mode (high-impedance state).
* This specification is subject to be changed without notice. 8.11.1999
B3-12

12 Page





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