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PDF EM6A9320 Data sheet ( Hoja de datos )
| Número de pieza | EM6A9320 | |
| Descripción | 4M x 32 DDR SDRAM | |
| Fabricantes | Etron Technology Inc. | |
| Logotipo |  |
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Et r onT ec h
Etron Confidential
Features
EM6A9320
4M x 32 DDR SDRAM
Preliminary (Rev 0.3 7/2002)
Overview
• Fast clock rate: 350/333/300/285/250/200 MHz
• Differential Clock CK & CK# input
• 4 Bi-directional DQS. Data transactions on both
edges of DQS (1DQS / Byte)
• DLL aligns DQ and DQS transitions
• Edge aligned data & DQS output
• Center aligned data & DQS input
• 4 internal banks, 1M x 32-bit for each bank
• Programmable mode and extended mode registers
- CAS# Latency: 3, 4, 5
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleave
• Full page burst length for sequential type only
• Start address of full page burst should be even
• All inputs except DQ’s & DM are at the positive
edge of the system clock
• No Write-Interrupted by Read function
• 4 individual DM control for write masking only
• Auto Refresh and Self Refresh
• 4096 refresh cycles / 32ms
• Power supplies up to 350/333/300/285MHz:
VDD = 2.8V ± 5%
VDDQ = 2.8V ± 5%
• Power supplies up to 250/200MHz:
VDD = 2.5V ± 5%
The EM6A9320 DDR SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 128
Mbits. It is internally configured as a quad 1M x 32
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal, CK).
Data outputs occur at both rising edges of CK and CK#.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence.
Accesses begin with the registration of a BankActivate
command, which is then followed by a Read or Write
command.
The EM6A9320 provides programmable Read or Write
burst lengths of 2, 4, 8. An auto precharge function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The refresh functions, either Auto or Self Refresh are
easy to use.
In addition, EM6A9320 features programmable DLL
option. By having a programmable mode register and
extended mode register, the system can choose the
most suitable modes to maximize its performance.
These devices are well suited for applications requiring
high memory bandwidth, result in a device particularly
well suited to high performance main memory and
graphics applications.
VDDQ = 2.5V ± 5%
• Interface : SSTL_2 I/O compatible
• 6WDQGDUG EDOO )%*$ SDFNDJH
Ordering Information
Part Number
EM6A9320BI-2.8
EM6A9320BI-3.0
EM6A9320BI-3.3
EM6A9320BI-3.5
EM6A9320BI-4
EM6A9320BI-5
Frequency
350MHz
333MHz
300MHz
285MHz
250MHz
200MHz
Power Supply
VDD 2.8V
VDDQ 2.8V
VDD 2.5V
VDDQ 2.5V
Package
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
1 page  
Et r onT ec h
4Mx32 DDR SDRAM
EM6A9320
VSS Supply Ground: Ground IRU WKH LQSXW EXIIHUV DQG FRUH ORJLF
VDDQ
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
VSSQ
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
VREF
Supply Reference Voltage for Inputs: +0.5 x VDDQ
NC - No Connect: These pins should be left unconnected.
Note: The timing reference point for the differential clocking is the cross point of the CK and CK#. For any
applications using the single ended clocking, apply VREF to CK# pin.
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK . Table 2 shows
the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State CKEn-1 CKEn DM BA1 BA0 A8 A11-A9, A7-0 CS# RAS# CAS# WE#
BankActivate
Idle(3)
H X X V V Row Address L L H H
BankPrecharge
Any H X X V V L X L L H L
PrechargeAll
Any
H X XXXH
X
LL HL
Write
Active(3) H X V V V L
LH LL
Write and AutoPrecharge
Active(3)
H
X
V
V
V
H
Column
Address
L
H
LL
Read
Active(3)
H
X X V V L A0~A7 L H
LH
Read and Autoprecharge Active(3) H X X V V H
LH LH
Mode Register Set
Extended Mode Register Set
Idle
Idle
H X XLL
H X XLH
OP code
LL
LL
LL
LL
No-Operation
Any H X X X X X X L H H H
Device Deselect
Any H X X X X X X H X X X
Burst Stop
Active(4) H X X X X X X L H H L
AutoRefresh
Idle H H X X X X X L L L H
SelfRefresh Entry
Idle H L X X X X X L L L H
SelfRefresh Exit
Idle H X X X
(Self Refresh) L
H XXXX
X
LH HH
Power Down Mode Entry Idle/Active(5) H
L XXXX
X
HX XX
LH HH
Power Down Mode Exit
Any
L H XXXX X H X X X
(Power Down)
LH HH
Data Write/Output Enable
Active
H X LXXX
X
XX XX
Data Mask/Output Disable
Active
H X HXXX
X
XX XX
Note:
1. V = Valid data, X = Don't Care, L = Low level, H = High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA0, BA1signals.
4. Read burst stop with BST command for all burst types.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
Etron Confidential
5
Rev 0.3
July. 2002
5 Page 
Et r onT ec h
4Mx32 DDR SDRAM
EM6A9320
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 2.8V ± 5% for 350, 333, 300, or 285MHz, VDD=2.5 ± 5% for 250 or 200MHz, TA = 0~70 °C)
Symbol
Parameter
2.8 3.0 3.3 3.5
Min Max Min Max Min Max Min Max
4.0
Min Max
5.0
Unit
Min Max
tCK Clock cycle time
CL = 3 3.3 10 3.3 10 3.3 10 3.5 10 4 10 5 10
CL = 4 2.86 10 3.0 10 3.3 10 3.5 10 4 10 5 10 ns
CL = 5 2.86 5 3.0 5 3.3 5 3.5 5 4 5 5 10
tCH Clock high level width
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
tCL Clock low level width
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
tDQSCK DQS-out access time from CK,CK#
-0.6 0.6 -0.6 0.6 -0.6 0.6 -0.6 0.6 -0.7 0.7 -0.7 0.7 ns
tAC Output access time from CK,CK# -0.6 0.6 -0.6 0.6 -0.6 0.6 -0.6 0.6 -0.7 0.7 -0.7 0.7 ns
tDQSQ DQS-DQ Skew
- 0.35 - 0.35 - 0.35 - 0.4 - 0.4 - 0.45 ns
tRPRE Read preamble
0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK
tRPST Read postamble
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
tDQSS CK to valid DQS-in
0.85 1.15 0.85 1.15 0.85 1.15 0.85 1.15 0.85 1.15 0.85 1.15 tCK
tWPRES DQS-in setup time
0 - 0 - 0 - 0 - 0 - 0 - ns
tWPREH DQS-in hold time
0.35 - 0.35 - 0.35 - 0.35 - 0.35 - 0.35 - ns
tWPST DQS write postamble
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
tDQSH DQS in high level pulse width
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
tDQSL DQS in low level pulse width
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
tIS Address and Control input setup time 0.9 - 0.9 - 0.9 - 0.9 - 0.9 - 1.0 - ns
tIH Address and Control input hold time 0.9 - 0.9 - 0.9 - 0.9 - 0.9 - 1.0 - ns
tDS DQ & DM setup time to DQS
0.35 - 0.35 - 0.35 - 0.4 - 0.45 - 0.5 - ns
tDH DQ & DM hold time to DQS
0.35 - 0.35 - 0.35 - 0.4 - 0.45 - 0.5 - ns
tHP Clock half period
tCLMIN
tCLMIN
tCLMIN
tCLMIN
tCLMIN
tCLMIN
or - or - or - or - or - or -
tCHMIN
tCHMIN
tCHMIN
tCHMIN
tCHMIN
tCHMIN
ns
tQH Output DQS valid window
tHP -
0.35
-
tHP -
0.35
-
tHP -
0.35
-
tHP -
0.4
-
tHP -
0.45
-
tHP -
0.5
-
ns
tRC Row cycle time
20 - 20 - 17 - 16 - 15 - 12 - tCK
tRFC
Refresh row cycle time
22 - 22 - 19 - 18 - 17 - 14 - tCK
tRAS
Row active time
14 100K 14 100K 12 100K 11 100K 10 100K 8 100K tCK
tRCDRD RAS# to CAS# Delay in Read
7 - 7 - 6 - 5 - 5 - 4 - tCK
tRCDWR RAS# to CAS# Delay in Write
5 - 5 - 4 - 3 - 3 - 2 - tCK
tRP Row precharge time
6 - 6 - 5 - 3 - 3 - 3 - tCK
tRRD
Row active to Row active delay
4 - 4 - 3 - 3 - 3 - 2 - tCK
twR Write recovery time
3 - 3 - 3 - 3 - 3 - 2 - tCK
tCDLR Last data in to Read command
2 - 2 - 2 - 2 - 2 - 2 - tCK
tCCD
Col. Address to Col. Address delay
1 - 1 - 1 - 1 - 1 - 1 - tCK
tMRD
Mode register set cycle time
1 - 1 - 1 - 1 - 2 - 2 - tCK
tDAL
Auto precharge write recovery + Precharge
9 - 9 - 9 - 9 - 8 - 7 - tCK
tXSA
Self refresh exit to read command delay
200 - 200 - 200 - 200 - 200 - 200 - tCK
tPDEX Power down exit time
tIS +
2tCK
-
tIS +
2tCK
-
tIS +
2tCK
-
tIS +
2tCK
-
tIS +
2tCK
-
tIS +
2tCK
-
ns
tREF
Refresh interval time
- 7.8 - 7.8 - 7.8
7.8 - 7.8
7.8 us
Etron Confidential
11
Rev 0.3
July. 2002
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet EM6A9320.PDF ] | |
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