EM658160TS-5 Datasheet PDF ( Pinout ) - 4M x 16 DDR Synchronous DRAM (SDRAM)

EM658160TS-5 Datasheet PDF - Etron Technology Inc.

Part Number	*EM658160TS-5*
Description	4M x 16 DDR Synchronous DRAM (SDRAM)
Manufacturers	Etron Technology Inc.
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Et r onT ec h

EM658160

Etron Confidential

4M x 16 DDR Synchronous DRAM (SDRAM)

(Rev. 1.1 Jan./2002)

Features

Pin Assignment (Top View)

• Fast clock rate: 300/285/250/200/166/143/125MHz

• Differential Clock CK & /CK

• Bi-directional DQS

• DLL enable/disable by EMRS

• Fully synchronous operation

• Internal pipeline architecture

• Four internal banks, 1M x 16-bit for each bank

• Programmable Mode and Extended Mode registers

- /CAS Latency: 2, 2.5, 3

- Burst length: 2, 4, 8

- Burst Type: Sequential & Interleaved

• Individual byte write mask control

• DM Write Latency = 0

• Auto Refresh and Self Refresh

• 4096 refresh cycles / 64ms

• Precharge & active power down

• Power supplies: VDD = 3.3V ± 0.3V

VDDQ = 2.5V ± 0.2V

• Interface: SSTL_2 I/O Interface

• Package: 66 Pin TSOP II, 0.65mm pin pitch

Ordering Information

Part Number

EM658160TS-3.3

EM658160TS-3.5

EM658160TS-4

EM658160TS-5

EM658160TS-6

EM658160TS-7

EM658160TS-8

Frequency

300MHz

285MHz

250MHz

200MHz

166MHz

143MHz

125MHz

Package

TSOP II

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDDQ

LDQS

VDD

LDM

/WE

/CAS

/RAS

/CS

BS0

BS1

A10/AP

VDD

66 VSS

65 DQ15

64 VSSQ

63 DQ14

62 DQ13

61 VDDQ

60 DQ12

59 DQ11

58 VSSQ

57 DQ10

56 DQ9

55 VDDQ

54 DQ8

53 NC

52 VSSQ

51 UDQS

50 NC

49 VREF

48 VSS

47 UDM

46 /CK

45 CK

44 CKE

43 NC

42 NC

41 A11

40 A9

39 A8

38 A7

37 A6

36 A5

35 A4

34 VSS

Overview

The EM658160 SDRAM is a high-speed CMOS

double data rate synchronous DRAM containing 64

Mbits. It is internally configured as a quad 1M x 16

DRAM with a synchronous interface (all signals are

registered on the positive edge of the clock signal, CK).

Data outputs occur at both rising edges of CK and /CK.

Read and write accesses to the SDRAM are burst

oriented; accesses start at a selected location and

continue for a programmed number of locations in a

programmed sequence. Accesses begin with the

registration of a BankActivate command which is then

followed by a Read or Write command. The EM658160

provides programmable Read or Write burst lengths of 2,

4, 8, full page.

An auto precharge function may be enabled to

provide a self-timed row precharge that is initiated at the

end of the burst sequence. The refresh functions, either

Auto or Self Refresh are easy to use. In addition,

EM658160 features programmable DLL option. By

having a programmable mode register and extended

mode register, the system can choose the most suitable

modes to maximize its performance. These devices are

well suited for applications requiring high memory

bandwidth, result in a device particularly well suited to

high performance main memory and graphics

applications.

Etron Technology, Inc.

No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.

TEL: (886)-3-5782345 FAX: (886)-3-5778671

Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.

Et r onT ec h

4Mx16 DDR SDRAM

EM658160

Operation Mode

Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 2

shows the truth table for the operation commands.

Table 2. Truth Table (Note (1), (2) )

Command

State CKEn-1 CKEn DM BS0,1 A10 A0-9,11 /CS /RAS /CAS /WE

BankActivate

Idle(3)

X X V Row address L L H H

BankPrecharge

Any H X X V L X L L H L

PrechargeAll

Any

X X XH

LL H L

Write

Write and AutoPrecharge

Active(3)

X X V L Column L H L L

address

X X V H (A0 ~ A7) L H L L

Read

Read and Autoprecharge

Active(3)

X X V L Column L H L H

address

X X V H (A0 ~ A7) L H L H

Mode Register Set

Idle H X X

OP code

LL L L

Extended MRS

Idle H X X

OP code

LL L L

No-Operation

Any H X X X X X L H H H

Burst Stop

Active(4) H X X X X X L H H L

Device Deselect

Any H X X X X X H X X X

AutoRefresh

Idle H H X X X X L L L H

SelfRefresh Entry

Idle H L X X X X L L L H

SelfRefresh Exit

Idle L H X X X X H X X X

(SelfRefresh)

LH H H

Clock Suspend Mode Entry

Active H L X X X X X X X X

Power Down Mode Entry

Any(5)

L X XX

HX X X

LH H H

Clock Suspend Mode Exit

Active L H X X X X X X X X

Power Down Mode Exit

Any L H X X X X H X X X

(PowerDown)

LH H H

Data Write/Output Enable

Active H X L X X X X X X X

Data Mask/Output Disable

Active H X H X X X X X

Note:

1. V=Valid data, X=Don't Care, L=Low level, H=High level

2. CKEn signal is input level when commands are provided.

CKEn-1 signal is input level one clock cycle before the commands are provided.

3. These are states of bank designated by BS signal.

4. Device state is 1, 2, 4, 8, and full page burst operation.

5. Power Down Mode can not enter in the burst operation.

When this command is asserted in the burst cycle, device state is clock suspend mode.

Etron Confidential

Rev. 1.1

Jan. 2002

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EM658160TS-5 Datasheet PDF - Etron Technology Inc.

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