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EM658160TS-33 Schematic ( PDF Datasheet ) - Etron Technology Inc.

Teilenummer EM658160TS-33
Beschreibung 4M x 16 DDR Synchronous DRAM (SDRAM)
Hersteller Etron Technology Inc.
Logo Etron Technology  Inc. Logo 




Gesamt 26 Seiten
EM658160TS-33 Datasheet, Funktion
Et r onT ec h
EM658160
Etron Confidential
4M x 16 DDR Synchronous DRAM (SDRAM)
(Rev. 1.1 Jan./2002)
Features
Pin Assignment (Top View)
Fast clock rate: 300/285/250/200/166/143/125MHz
Differential Clock CK & /CK
Bi-directional DQS
DLL enable/disable by EMRS
Fully synchronous operation
Internal pipeline architecture
Four internal banks, 1M x 16-bit for each bank
Programmable Mode and Extended Mode registers
- /CAS Latency: 2, 2.5, 3
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
Individual byte write mask control
DM Write Latency = 0
Auto Refresh and Self Refresh
4096 refresh cycles / 64ms
Precharge & active power down
Power supplies: VDD = 3.3V ± 0.3V
VDDQ = 2.5V ± 0.2V
Interface: SSTL_2 I/O Interface
Package: 66 Pin TSOP II, 0.65mm pin pitch
Ordering Information
Part Number
EM658160TS-3.3
EM658160TS-3.5
EM658160TS-4
EM658160TS-5
EM658160TS-6
EM658160TS-7
EM658160TS-8
Frequency
300MHz
285MHz
250MHz
200MHz
166MHz
143MHz
125MHz
Package
TSOP II
TSOP II
TSOP II
TSOP II
TSOP II
TSOP II
TSOP II
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BS0
BS1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66 VSS
65 DQ15
64 VSSQ
63 DQ14
62 DQ13
61 VDDQ
60 DQ12
59 DQ11
58 VSSQ
57 DQ10
56 DQ9
55 VDDQ
54 DQ8
53 NC
52 VSSQ
51 UDQS
50 NC
49 VREF
48 VSS
47 UDM
46 /CK
45 CK
44 CKE
43 NC
42 NC
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
Overview
The EM658160 SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 64
Mbits. It is internally configured as a quad 1M x 16
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal, CK).
Data outputs occur at both rising edges of CK and /CK.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the
registration of a BankActivate command which is then
followed by a Read or Write command. The EM658160
provides programmable Read or Write burst lengths of 2,
4, 8, full page.
An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the
end of the burst sequence. The refresh functions, either
Auto or Self Refresh are easy to use. In addition,
EM658160 features programmable DLL option. By
having a programmable mode register and extended
mode register, the system can choose the most suitable
modes to maximize its performance. These devices are
well suited for applications requiring high memory
bandwidth, result in a device particularly well suited to
high performance main memory and graphics
applications.
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.






EM658160TS-33 Datasheet, Funktion
Et r onT ec h
4Mx16 DDR SDRAM
EM658160
Mode Register Set (MRS)
The mode register is divided into various fields depending on functionality.
Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the
Burst Length to be 2, 4, 8.
A2 A1 A0 Burst Length
0 0 0 Reserved
001
2
010
4
011
8
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, both Interleave Mode or Sequential Mode.
Both Sequential Mode and Interleave Mode support burst length of 2,4 and 8.
A3 Addressing Mode
0 Sequential
1 Interleave
--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column
address which is input to the device. The internal column address is varied by the Burst
Length as shown in the following table.
Data n
0 1234567
Column Address n n+1 n+2 n+3 n+4 n+5 n+6 n+7
2 words
Burst Length
4 words
8 words
Full Page (Even starting address)
--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the
address bits in the sequence shown in the following table.
Data n
Column Address
Data 0 A7 A6 A5 A4 A3 A2 A1 A0
Data 1 A7 A6 A5 A4 A3 A2 A1 A0#
Data 2 A7 A6 A5 A4 A3 A2 A1# A0
Data 3 A7 A6 A5 A4 A3 A2 A1# A0#
Data 4 A7 A6 A5 A4 A3 A2# A1 A0
Data 5 A7 A6 A5 A4 A3 A2# A1 A0#
Data 6 A7 A6 A5 A4 A3 A2# A1# A0
Data 7 A7 A6 A5 A4 A3 A2# A1# A0#
Burst Length
4 words
8 words
Etron Confidential
6
Rev. 1.1
Jan. 2002

6 Page









EM658160TS-33 pdf, datenblatt
Et r onT ec h
4Mx16 DDR SDRAM
EM658160
Timing Waveforms
Figure 1. AC Parameters for Read Timing (Burst Length=4, CAS Latency=2.5)
tCH tCL
CK
/CK
CMD
ADDR
tIS tIH
Read
tIS tIH
/CS
DQS
DQ
tCK
tDQSQ
tRPRE
tRPST
Preamble
Postamble
tAC
D0 D1 D2 D3
Etron Confidential
12
Rev. 1.1
Jan. 2002

12 Page





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