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Número de pieza | EM639165 | |
Descripción | 8Mega x 16bits SDRAM | |
Fabricantes | Etron Technology Inc. | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de EM639165 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! EtronTech
EM639165
8M x 16 bit Synchronous DRAM (SDRAM)
Advanced (Rev. 2.3, Dec. /2013)
Features
• Fast access time from clock: 4.5/5/5.4 ns
• Fast clock rate: 200/166/143 MHz
• Fully synchronous operation
• Internal pipelined architecture
• 2M word x 16-bit x 4-bank
• Programmable Mode registers
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst stop function
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• CKE power down mode
• Single +3.3V ± 0.3V power supply
• Industrial Temperature: -40~85°C
• Interface: LVTTL
• 54-pin 400 mil plastic TSOP II package
- Pb free and Halogen free
• 54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package
- Pb free and Halogen free
Overview
The EM639165 SDRAM is a high-speed CMOS
synchronous DRAM containing 128 Mbits. It is
internally configured as 4 Banks of 2M word x 16
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CLK). Read and write accesses to the SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with
the registration of a BankActivate command which
is then followed by a Read or Write command.
The EM639165 provides for programmable
Read or Write burst lengths of 1, 2, 4, 8, or full page,
with a burst termination option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use.
By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth and particularly well suited to high
performance PC applications.
Table1. Key Specifications
EM639165
tCK3 Clock Cycle time(min.)
tAC3 Access time from CLK(max.)
tRAS Row Active time(min.)
tRC Row Cycle time(min.)
-5I/6I/7I
5/6/7
4.5/5/5.4
40/42/42
55/60/63
ns
ns
ns
ns
Table 2. Ordering Information
Part Number
EM639165TS -5IG
Frequency
200MHz
Package
TSOPII
EM639165TS -6IG
166MHz
TSOPII
EM639165TS -7IG
EM639165BM -5IH
143MHz
200MHz
TSOPII
FBGA
EM639165BM -6IH
166MHz
FBGA
EM639165BM -7IH
143MHz
FBGA
TS: indicates TSOPII Package
BM: indicates 8.0 x 8.0 x 1.2mm FBGA Package
I: indicates Industrial Grade
G: indicates Pb and Halogen Free for TSOPII Package
H: indicates Pb free and Halogen Free for FBGA Package
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc. reserves the right to change products or specification without notice.
1 page EtronTech
EM639165
LDQM,
UDQM
DQ0-DQ15
NC/RFU
VDDQ
VSSQ
VDD
VSS
Input
Input /
Output
-
Supply
Supply
Supply
Supply
Data Input/Output Mask: Controls output buffers in read mode and masks
Input data in write mode.
Data I/O: The DQ0-15 input and output data are synchronized with the positive
edges of CLK. The I/Os are maskable during Reads and Writes.
No Connect: These pins should be left unconnected.
DQ Power: Provide isolated power to DQs for improved noise immunity.
( 3.3V± 0.3V )
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
(0V)
Power Supply: +3.3V ± 0.3V
Ground
Rev. 2.3
5 Dec. /2013
5 Page EtronTech
EM639165
CLK
COMMAND
T0 T1 T2 T3 T4 T5 T6 T7 T8
NOP
WRITE A READ B
NOP
NOP
NOP
NOP
NOP
NOP
CAS# Latency=2
tCK2, DQ
DIN A0
don’t care
DOUT B0 DOUT B1 DOUT B2 DOUT B3
CAS# Latency=3
tCK3, DQ
DIN A0
don’t care
don’t care
DOUT B0 DOUT B1 DOUT B2 DOUT B3
Input data must be removed from the DQ at
least one clock cycle before the Read data
appears on the outputs to avoid data contention
Figure 13. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge
function should be issued m cycles after the clock edge in which the last data-in element is registered,
where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used
to mask input data, starting with the clock edge following the last data-in element and ending with the
clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure).
T0 T1 T2 T3 T4 T5 T6 T7
CLK
DQM
COMMAND
WRITE
NOP
NOP
Precharge
tRP
NOP
NOP
Activate
NOP
ADDRESS
DQ
Bank
Col n
DIN
n
tWR
DIN
N+1
Bank (s)
ROW
Don’t Care
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Figure 14. Write to Precharge
7 Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H", A0-A8
= Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the
write operation. Once this command is given, any subsequent command can not occur within a time
delay of {(burst length -1) + tWR + tRP (min.)}. At full-page burst, only the write operation is performed in
this command and the auto precharge function is ignored.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
CLK
COMMAND
Bank A
Activate
NOP
NOP
WRITE A
Auto Precharge
NOP
NOP
tDAL
NOP
NOP
NOP
DQ
DIN A0
DIN A1
tDAL=tWR+tRP
Begin AutoPrecharge
Bank can be reactivated at
completion of tDAL
Figure 15. Burst Write with Auto-Precharge (Burst Length = 2)
Bank A
Activate
Rev. 2.3
11 Dec. /2013
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet EM639165.PDF ] |
Número de pieza | Descripción | Fabricantes |
EM639165 | 8Mega x 16bits SDRAM | Etron Technology Inc. |
EM639165TS | 8M x 16 bit Synchronous DRAM | Etron Technology |
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