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PDF EM637327TQ-5 Data sheet ( Hoja de datos )
| Número de pieza | EM637327TQ-5 | |
| Descripción | 1Mega x 32 SGRAM | |
| Fabricantes | Etron Technology Inc. | |
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EtronTech
Features
• Fast access time from clock: 4.5/5.5/5.5/6 ns
• Fast clock rate: 200/166/143/125 MHz
• Fully synchronous operation
• Internal pipelined architecture
• Dual internal banks (512K x 32bit x 2bank)
• Programmable Mode
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst-Read-Single-Write
- Load Color or Mask register
• Burst stop function
• Individual byte controlled by DQM0-3
• Block write and write-per-bit capability
• Auto Refresh and Self Refresh
• 2048 refresh cycles/32ms
• Single +3.3V ± 0.3V power supply
• Interface: LVTTL
• JEDEC 100-pin Plastic package
- QFP (body thickness=2.8mm)
- TQFP1.4 (body thickness=1.4mm)
Key Specifications
EM637327
tCK3 Clock Cycle time(min.)
tRAS Row Active time(max.)
tAC3 Access time from CLK(max.)
tRC Row Cycle time(min.)
- 5/6/7/8
5/6/7/8 ns
25/30/35/40 ns
4.5/5.5/5.5/6 ns
55/60/63/72 ns
Ordering Information
Part Number
EM637327Q-5
EM637327TQ-5
EM637327Q-6
EM637327TQ-6
EM637327Q-7
EM637327TQ-7
EM637327Q-8
EM637327TQ-8
Frequency
200 MHz
200 MHz
166 MHz
166 MHz
143 MHz
143 MHz
125 MHz
125 MHz
Package
QFP
TQFP1.4
QFP
TQFP1.4
QFP
TQFP1.4
QFP
TQFP1.4
EM637327
1Mega x 32 SGRAM
Preliminary (08/99)
Pin Assignment (Top View)
DQ 3
VDDQ
DQ 4
DQ 5
VSSQ
DQ 6
DQ 7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DQM0
DQM2
WE#
CA S#
RA S#
CS 0#
BS
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80 DQ28
7 9 VDDQ
78 DQ27
77 DQ26
7 6 VSSQ
75 DQ25
74 DQ24
7 3 VDDQ
72 DQ15
71 DQ14
7 0 VSSQ
69 DQ13
68 DQ12
6 7 VDDQ
6 6 VSS
65 VDD
64 DQ11
63 DQ10
6 2 VSSQ
6 1 DQ 9
6 0 DQ 8
5 9 VDDQ
5 8 NC
57 DQM3
56 DQM1
5 5 CL K
5 4 CKE
53 DSF
5 2 NC
5 1 A8 (AP)
Overview
The EM637327 SGRAM is a high-speed CMOS
synchronous graphics DRAM containing 32 Mbits. It is
internally configured as a dual 512K x 32 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
512K x 32 bit banks is organized as 2048 rows by 256
columns by 32 bits. Read and write accesses to the
SGRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which
is then followed by a Read or Write command.
The EM637327 provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use.
By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth.
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
1 page  
EtronTech
1Mega x 32 SGRAM EM637327
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State CKEn-1 CKEn DQM(7) BS A8 ADDR CS# RAS# CAS# WE# DSF
BankActivate & Masked Write Disable Idle(3) H X X V V V L L H H L
BankActivate & Masked Write Enable Idle(3) H X X V V V L L H H H
BankPrecharge
Any H X X V L X L L H L L
PrechargeAll
Any H X X X H X L L H L L
Write
Active(3) H X X V L V L H L L L
Block Write Command
Active(3) H X X V L V L H L L H
Write and AutoPrecharge
Active(3) H X X V H V L H L L L
Block Write and AutoPrecharge
Active(3) H X X V H V L H L L H
Read
Active(3) H X X V L V L H L H L
Read and Autoprecharge
Active(3) H X X V H V L H L H L
Mode Register Set
Idle H X X V L V L L L L L
Special Mode Register Set
Idle(5) H X X X X V L L L L H
No-Operation
Any H X X X X X L H H H X
Burst Stop
Active(4) H X X X X X L H H L L
Device Deselect
Any H X X X X X H X X X X
AutoRefresh
Idle H H X X X X L L L H L
SelfRefresh Entry
Idle H L X X X X L L L H L
SelfRefresh Exit
Idle L H X X X X H X X X X
(SelfRefresh)
L H H HX
Clock Suspend Mode Entry
Active H L X X X X X X X X X
Power Down Mode Entry
Any(6) H L X X X X H X X X X
L H H HL
Clock Suspend Mode Exit
Active L H X X X X X X X X X
Power Down Mode Exit
Any L H X X X X H X X X X
(PowerDown)
L H H HL
Data Write/Output Enable
Active H X L X X X X X X X X
Data Mask/Output Disable
Active H X H X X X X X X
Note:
1. V=Valid X=Don't Care L=Low level H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. The Special Mode Register Set is also available in Row Active State.
6. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
7. DQM0-3
X
X
Preliminary
5 August 1999
5 Page 
EtronTech
1Mega x 32 SGRAM EM637327
first read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
T0 T1
T2 T3
T4 T5
T6 T7
T8
CLK
COM MAND
NOP
WRITE A READ B
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
DIN A0
DOUT B0 DOUT B1
DOUT B2 DOUT B3
DIN A0
don't care
DOUT B0
DOUT B1
DOUT B2 DOUT B3
DIN A0
don't care don't care
Input data for the write is masked.
DOUT B0
DOUT B1 DOUT B2 DOUT B3
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
T0 T1
T2 T3 T4 T5
T6
CLK
DQM
C OM M A ND
WRITE
NOP
Precharge
tRP
NOP NOP
Activate
NOP
ADDRESS
DQ
BANK
COL n
DIN
n
BANK (S)
tWR
DIN
n+1
ROW
: don't care
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
When the Burst-Read-Single-Write mode is selected, the write burst length is 1 regardless of
the read burst length (refer to Figures 21 and 22 in Timing Waveforms).
8 Block Write command
(RAS# = "H", CAS# = "L", WE# = "L", DSF = "H", BS = Bank, A8 = "L", A3-A7 = Column Address,
DQ0-DQ31 = Column Mask)
The block writes are non-burst accesses that write to eight column locations simultaneously. A
single data value, which was previously loaded in the Color register, is written to the block of eight
consecutive column locations addressed by inputs A3~A7. The information on the DQs which are
Preliminary
11 August 1999
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet EM637327TQ-5.PDF ] | |
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